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参数资料
| 型号： | ST5451D |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO28 |
| 封装： | SO-28 |
| 文件页数： | 10/34页 |
| 文件大小： | 269K |
| 代理商： | ST5451D |
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4 - 8 - 2 - M CHANNELS INTERRUPTS EOM,
RMR, XMR, RAB
Receive Direction
RMR 1/2 is a bit of interrupt register ISTA 1/2
coming high to indicate the M (or M’) channel
controller has received a valid byte on receiving
channel (two identical consecutive bytes).
The microprocessor processing order is;
1. Erasing RMR 1/2 interrupt into ISTA 1/2
2. Read MONR 1/2 register.
This order can’t be inverted because, as long as
MONR isn’t read, the receive state machine is
locked in wait state, a new byte can’t be acknow-
ledged and so, a new interrupt can’t be done.
More, if MONR is read first, the receive state ma-
chine is ready for receiving a new byte and create
another interrupt. So, if the interrupt bit corre-
sponding to the previous frame isn’t erased be-
fore a new byte arrives, this byte won’t be seen
(the microprocessor won’t be informed) and the
controller will be locked waiting for MONR read.
XAB 1/2 is a bit of the interrupt register coming
high to indicate the receive controller has de-
tected an abort (two conscutive bytes not identi-
cal) as long as this interrupt isn’t erased, the re-
ceiver is locked in wait state.
EOM 1/2 is a bit of the interrupt register coming
high to indicate the receive controller has de-
tected an end of message. As long as the inter-
rupt isn’t erased, the receiver is locked in wait
state.
Transmit Direction
XMR 1/2 is a bit of the interrupt register coming
high to indicate a byte can be written into MONX.
The processing order is:
1. Erasing XMR bit
2. Writing a new byte into MONX.
If this order is inverted, the new byte will be trans-
mitted and a new XMR may be erased before be-
ing seen by the microprocessor.
RAB 1/2 is a bit of the interrupt register coming
high to indicate the remote receiver has reported
an abort detection. The processing order is:
1. Erasing RAB bit
2. Erasing XMR bit
3. Writing a new byte into MONX.
If a write operation of the new byte is done before
the RAB erasing, the byte will be lost and the
transmitter will stay waiting for it.
4 - 8 - 3 - CI CHANNEL INTERRUPTS
CIC 1/2 is a bit of ISTA 1/2 interrupt register com-
ing high to indicate a valid byte has been de-
tected by the command indicate receive control-
ler, and readable into CIR 1/2 register. The
processing order is:
1. Erasing CIC bit
2. Reading CIR register.
If this order is inverted, a next byte may be un-
seen by the microprocessor. It is recommended
to work with ”Ping Pong” protocol on CI channels,
as non flow control is done.
4 - 9 - SOFTWARE RESET PROCEDURES
4 - 9 - 1 - XRES (Transmit Direction)
XRES is a level sensitive command of CMDR
which initialize the transmit process.
- XPR interrupt bit is erased
- XDU interrupt bit is not erased (security pro-
cedure)
- All data in FIFOs are lost
- After an XRES, the microprocessor must wait
for an XPR before writing new data.
The processing order is:
- Writing a ”1” into XRES (CMDR)
- Writing a ”0” into XRES (CMDR)
- Read ISTA0 waiting XPR or enable XPR in-
terrupt
4 - 9 - 2 - RHR (Receive Direction)
RHR is a level sensitive command of CMDR,
which reinitialize the receive process.
- RME, RPF bits are erased
- RFO bit is erased
- All frames in FIFO R are lost
- If RHR is released (got down) at the time a
frame is on line, the HDLC controller waits
for a flag.
4 - 9 - 3 - M1RES, M2RES M/CI channels
MRES is a level sensitive command of CMDR
which initialize the M/CI channel protocole in both
directions.
XMR, RAB, RMR, CIC, XAB, EOM bits are
erased by MRES.
After a clock programming (bit CRS), it’s neces-
sary to put MRES bit to initialize properly the M
protocol.
ST5451
18/34
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST5451L | 制造商:Valor 功能描述: |
| ST5451N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ISDN， Other/Special/Miscellaneous |
| ST5452L | 制造商:Pulse 功能描述:- Bulk |
| ST5453L | 制造商:Pulse 功能描述:- Bulk |
| ST5454L | 制造商:Pulse 功能描述:- Bulk |
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