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参数资料
| 型号： | ST5451D |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO28 |
| 封装： | SO-28 |
| 文件页数： | 23/34页 |
| 文件大小： | 269K |
| 代理商： | ST5451D |
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DEMULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 0)
NAME
PIN
TYPE
FUNCTION
A0/A5
3-8
I
Address Bus. To transfer addresses from
P to ST5451.
D0/D7
17-24
I/O
Data Bus. To transfer data between
P and ST5451.
R/W
27
I
Read/Write. ”1” indicates a read operation; ”0” a write operation.
E26
I
Enable. Read/write operations are synchronized with this signal; its
falling edge marks the end of an operation.
MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 1 I/M=1)
NAME
PIN
TYPE
FUNCTION
AD0/AD7
17-24
I/O
Address Data Bus. To transfer addresses and data between
P
and ST5451.
WR
27
I
Write. This signal indicates a write operation.
RD
26
I
Read. This signal indicates a read operation.
ALE
3
I
Falling edge latches the address from the external A/D Bus.
MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 1; I/M= 0)
NAME
PIN
TYPE
FUNCTION
AD0/AD7
17-24
I/O
Address Data Bus. To transfer addresses and data between
P
and ST5451.
R/W
27
I
Read/Write. ”1” Indicates a write operation; ”0” a write operation.
DS
26
I
Data Strobe. Read/Write operations are synchronized with this
signal: its falling edge marks the end of an operation.
AS
3
I
Address Strobe. Falling edge latches the address from the external
A/D Bus.
DMA (direct memory access): only when MULT = 1
NAME
PIN
TYPE
FUNCTION
DMA REQ X
DMA REQ R
7
5
O
Direct Memory Access Requests: these outputs are asserted by
the device to request an exchange of byte from the memory.
DMA ACK X
DMA ACK R
8
6
I
Direct Memory Access Acknowledge: these inputs are asserted by
the DMA controller to signal to the HDLC controller that a byte is
being transferred in response to a previous transfer request.
GCI INTERFACE
NAME
PIN
TYPE
FUNCTION
DOUT
15
I/O
Data output for B and D channels. In GCI mode it outputs B1,
B2, M and C/I channels. In TE mode (GCI-SCIT) it can invert to
input data for M’ and C/I’ channels (See Table 2).
DIN
12
I/O
Data input for B and D channels. In GCI mode it inputs B1, B2, M
and C/I channels. In TE mode (GCI-SCIT) it can invert to output
data for M’ and C/I’ channels (See Table 2).
CLK
11
I
Data Clock. It determines the data shift rate for GCI channels on
the module interface.
FS
13
I
Frame synchronization. This signal is a 8 kHz signal for frame
synchronization. The front edge gives the time reference of the first
bit in the frame.
DEN
10
I
Data Enable. In TE mode, this pin is a normally low input pulsing
high to indicate the active bit times for D channel transmit at DOUT
pin. It is intended to be gated with CLK to control the shifting of
data from HDLC controller to S interface device.
ST5451
3/34
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST5451L | 制造商:Valor 功能描述: |
| ST5451N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ISDN， Other/Special/Miscellaneous |
| ST5452L | 制造商:Pulse 功能描述:- Bulk |
| ST5453L | 制造商:Pulse 功能描述:- Bulk |
| ST5454L | 制造商:Pulse 功能描述:- Bulk |
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