- 您现在的位置：买卖IC网 > PDF目录69348 > ST5451D (STMICROELECTRONICS) 1 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO28 PDF资料下载
参数资料
| 型号： | ST5451D |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO28 |
| 封装： | SO-28 |
| 文件页数： | 9/34页 |
| 文件大小： | 269K |
| 代理商： | ST5451D |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
4 - 8 - INTERRUPT PROCEDURE
4 - 8 - 1 - HDLC CHANNELS
4 - 8 - 1 - 1 - RECEIVE DIRECTION
RRE and RPF interrupts
RPF bit (register ISTA0) set high to indicate the
HDLC controller has received a block of 32 bytes
which is not a complete message.
This bit remains high until it is erased by the mi-
croprocessor.
As for each bit of ISTA0 register, except the ex-
tension bits of ISTA1 and ISTA2 (EXI1, EXI2), the
way to erase RPF is to write a ”0” at its location
and to write a ”1” at the location of the others (for
example 7FH into ISTA0 to erase RME). The
processing order is:
- put Mask0 on ISTA0 (if Mask Off)
- (Read FIFOR) X 32
- Write ISTA0 to erase RPF (BFH)
- Write RMC to ”1” for asking for another block
of the frame
(NB: RMC, RMD are automatically erased
by the controller)
- Remove Mask0
RME bit (register ISTA0) set high to indicate the
HDLC controller has received a short frame or the
last block of a large frame. The message is now
complete, the bit remains high until it is erased by
the microprocessor. The processing order is:
- put Mask0 on ISTA0 (if upper level Mask Off)
- Read RFBC with a mask on the 3 most sig-
nificant bits, to know the number ”N” of
transfers to do
- (Read FIFOR) x N for data
- Read FIFOR for status on the frame
- Write ISTA0 to erase RME (7FH)
- Write RMC or RMD to ”1” for asking for an-
other frame.
RF0 interrupts
RF0 is a bit of the interrupt register ISTA0 set
high to indicate an overflow of the receive FIFO
has been detected, either because more than 8
frames cannot be stored or because more than
64 bytes can’t be stored. This information is also
stored into the status of the concerned frame
(RDO).
The processing order of the microprocessor is:
- Looking for RPF and RME bits and pop - up
the frames. Then look for the status and
throw down the frame concerned. In general
case, only one frame is lost.
4 - 8 - 1 - 2 - TRANSMIT DIRECTION
XPR Interrupt
XPR is a bit of the interrupt register ISTA0 coming
high to indicate HDLC controller has a free block
of 32 bytes. This bit remains high until the micro-
processor write a byte into the block and erase
this bit into ISTA0; if another block is free, XPR
get high again immediately.
The processing order of the microprocessor is in
non DMA Mode:
- Put Mask0 on ISTA0 (if upper level Mask Off)
- Write at least one byte into FIFOX
- Write ISTA0 to erase XPR
- Write XHF to ”1” for launching the transmit
operation of block (a block is not necessarily
32 bytes)
or write XME to ”1” for launching the trans-
mit of a short frame or of the last part of a
frame
- Remove masks
In DMA Mode two general cases are possible:
1) The external DMA controller works by ”pages”
less or equal to 32 bytes. The ”process” of the
DMAC is a short frame transmission and the
processor must give an XME at the end of the
DMAC process (refer to figure 2).
2) The DMA controller works by ”pages” of more
than 32 bytes. It’s process is the transfer of the
whole frame.
The circuit doesn’t need an XHF at the end of an
intermediate 32 byte block; since it has reached
32 bytes written into the current fifo, it begins the
transfer and toggles on the second fifo as soon as
the first is full. (At this moment an XME is possi-
ble if the 32
nd byte was the end of the frame -
case 1) and then, a 33
rd write operation into the
fifo generates an internal XHF and the frame fol-
lowing blocks are expected.
- In the two cases the flow control is done be-
tween DMAC and ST5451 by the way of
REQX and ACKX signals
The processing order is:
- Put Mask0
- Give order to DMAC to begin transfer
- Wait for DMAC end of process
- Write ISTA to erase on XPR
- Write XME to signal the end of the frame to
the ST5451 (otherwise the ST5451 will put
”underrun” interrupt, as soon as its two
blocks are free).
XDU Interrupt
XDU is a bit of the interrupt register ISTA0 com-
ing high to indicate HDLC controller has detected
an underrun (a frame is being transmitted and no
more bytes are available into the FIFO).
The HDLC controller finish the frame by transmit-
ting an ”Abort” and no more data can be transmit-
ted even in NHF mode. To be sure XDU is seen
by the MIcroprocessor, XDU interrupt bit must be
erased in ISTA0 in addition of XRES security pro-
cedure
The transmit control is frozen and the only way to
reinitialize a transmit session is to write an XRES,
after erasing XDU.
ST5451
17/34
相关PDF资料 |
PDF描述 |
|---|---|
| ST6200CN1/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| ST6203CB3/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP16 |
| ST6201CN6/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| ST6201CM3/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| ST6201CM6/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST5451L | 制造商:Valor 功能描述: |
| ST5451N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ISDN， Other/Special/Miscellaneous |
| ST5452L | 制造商:Pulse 功能描述:- Bulk |
| ST5453L | 制造商:Pulse 功能描述:- Bulk |
| ST5454L | 制造商:Pulse 功能描述:- Bulk |
发布紧急采购，3分钟左右您将得到回复。