- 您现在的位置：买卖IC网 > PDF目录69348 > ST5451D (STMICROELECTRONICS) 1 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO28 PDF资料下载
参数资料
| 型号： | ST5451D |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO28 |
| 封装： | SO-28 |
| 文件页数： | 6/34页 |
| 文件大小： | 269K |
| 代理商： | ST5451D |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
4 - 3 - COMMAND/INDICATE PROCEDURE
The exchange of information in the C/I channel
runs as follows:
The two circuits (i.e. ST5421 and ST5451) con-
nected on the GCI interface send one each other
a permanent four bit command code in C/I field.
RECEIVE C/I
The ST5451 stores on every frame the four bits of
C/I channel coming from level 1 circuit in a first
register CIR. This value is compared with the pre-
vious one. If a one new appears during two con-
secutive frames, this new value is loaded in regis-
ter CIR1 and a CIC1 interrupt is generated.
TRANSMIT C/I
The transmit register CIX1 can be written at any
time by the
P. Its content is continuously sent in
the C/I channel.
Note: The TIM command (0000) forces a low
level on DOUT, if CIR1 = DI (1111) when VZ
DOUT = 1 to require FS and CLK.
4 - 4 - MONITOR CHANNEL
The GCI Monitor channel procedure allows full
duplex data transmission with acknowledgement
using A bit.
MESSAGE RECEIVING
An interrupt (bit RMR1 in ISTA1 register) is gen-
erated when a new byte is available in register
MONR1.
ST5451 generates an interrupt bit (XAB1 in
ISTA1) if it does not read twice the same bytes
meanwhile sending an ABORT to the remote
transmitter.
It performs an interrupt (EOM in ISTA1) also
when it has received an End Of Message. Ac-
knowledgement to remote transmitter is sent if:
- the byte was received twice with the same value
- the microprocessor reads the previous byte
stored in register MONR1.
This procedure performs flow control between S
interface device and
P.
MESSAGE TRANSMISSION
ST5451generates an interrupt (XMR1 in ISTA1)
when register MONX1 is available.
Writing register MONX1/0 generates a message
transmission. When the last byte is stored in the
register MONX1/1, ST5451 sends the End of
Message to remote receiver. If an Abort is re-
ceived, one interrupt (RAB1) is generated.
4 - 5 - M’ and C/I’ CHANNELS
The procedure allows a full duplex data transmis-
sion between microprocessor and the peripheral
devices connected on C/I’ local and M’ channel
through GCI-SCIT channel 1.
Receive Interrupt on C/I’ (DOUT is an input).
A new value on C/I’ indicates to ST5451 master
that one device in the terminal wants to send a
message. Up to six peripherals may generate
such an interrupt to the microprocessor.
ST5451 writes at every frame the six bits of C/I’
channel coming from peripherals in register CIR’.
This value is compared with the previous one and
if a new one appears during two consecutive
frames, is loaded in register CIR2 and CIC2 inter-
rupt (ISTA2 register) is generated.
P may send a message on M’ channel (DIN be-
comes an output) to allow the peripheral device to
transmit.
MESSAGE TRANSMISSION ON M’ CHANNEL
ST5451 sets interrupt XMR2 (ISTA2 register) if
register MONX2/0 is available. Writing MONX2/0
generates a message transmission. When the
last byte is stored in
register MONX2/1,
ST5451sends End of Message to remote periph-
eral.
If an ABORT is received, interrupt RAB2 (ISTA2
register) is issued. Then microprocessor may
send its message again.
MESSAGE RECEPTION ON M’ CHANNEL
Interrupt bit RMR2 (ISTA2 register) is generated
when a new byte is available in MONR2 register.
ST5451 sets interrupt bit XAB2 (ISTA2 register) if
it does not read twice the same byte; in this case,
it sends an ABORT to remote peripheral.
The controller generates interrupt bit EOM2
(ISTA2 register) when End Of Message is re-
ceived.
4 - 6 - ACCESS PROCEDURE TO D AND C/I
CHANNELS (GCI and TE mode selected only)
Up to eight HDLC controllers may be connected
to D channel and C/I channel. A contention reso-
lution mechanism is used if bit CMS (Contention
Mode Selection) is set.
The mechanism allows to give an access without
losing data.
An access request may be generated, if CIX1
(Command/Indicate Register 1) contains a differ-
ent code from DI (1111). During the procedure, M
channel (with A and E bits) may be used. On in-
put DIN, the GCI controller checks the CMS4 bit
(CMS channel - Third GCI channel) (see Fig. 4).
CMS4 indicates the status of C/I and D channels
CMS4= 1 ”channels free”; CMS4= 0 channels oc-
cupied.
If the channels are free, the HDLC controller
starts transmitting its individual address AD2 on
CMS1, AD1 on CMS2, AD0 on CMS3. If an erro-
neous address is detected, the procedure is ter-
minated immediately. If the complete address can
be read without error, the D and C/I channels are
occupied: the ST5451 transmits CMS4 = 0: The
HDLC controller which has the lowest address
has priority over the others.
The access request is withdrawn if the HDLC
controller transmits code DI = 1111. the CMS4 bit
(CMS field) is set.
ST5451
14/34
相关PDF资料 |
PDF描述 |
|---|---|
| ST6200CN1/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| ST6203CB3/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP16 |
| ST6201CN6/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| ST6201CM3/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| ST6201CM6/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST5451L | 制造商:Valor 功能描述: |
| ST5451N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ISDN， Other/Special/Miscellaneous |
| ST5452L | 制造商:Pulse 功能描述:- Bulk |
| ST5453L | 制造商:Pulse 功能描述:- Bulk |
| ST5454L | 制造商:Pulse 功能描述:- Bulk |
发布紧急采购，3分钟左右您将得到回复。