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参数资料
| 型号： | ST5x86 |
| 厂商： | 意法半导体 |
| 英文描述： | 100 and 120 MHz 3.45 Volt 5x86 CPU(微处理器) |
| 中文描述： | 100和120兆赫3.45伏特5x86的CPU（微处理器） |
| 文件页数： | 2/39页 |
| 文件大小： | 326K |
| 代理商： | ST5X86 |
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ST5x86
2/39
1.0 ARCHITECTURE OVERVIEW
The SGS-THOMSON 5x86 family represents a
new generation of x86-compatible 64-bit micropro-
cessors with fifth-generation features. The Branch
Target Buffer provides branch prediction with
accuracy
averaging
80%.
Load/Store unit allows multiple instructions in a
single clock cycle. Other features include sin-
gle-cycle
execution,
decode, 16-KByte Write-Back cache, and clock
rates up to 120 MHz made possible by the use of
advanced process technologies and superpipelin-
ing. The 100-MHz core speed option can operate
with a bus speed of either 33 MHz or 50 MHz. The
120-MHz core speed option operates with a bus
speed of 40 MHz.
The 5x86 CPU operates from a 3.45-volt power
supply, resulting in lower power consumption at all
clock frequencies. Where additional power sav-
ings are required (especially in portable applica-
tions), designers can make use of suspend mode,
stop clock capability, and System Management
Mode (SMM).
1.1 Major Functional Blocks
The 5x86 CPU is divided into major functional
blocks as shown in the overall block diagram on
the first page of thismanual.
- Integer Unit
- Floating Point Unit
- Write-Back Cache
- Memory Management Unit
- Bus Interface Unit
The Integer Unit consists of the
- Instruction Buffer
- Instruction Fetch Unit
- Instruction Decoder and Issue Unit.
Instructions are executed in the integer unit and in
the floating point unit. The cache unit stores the
most recently used data and instructions and pro-
vides fast access to this information for the integer
and floating point units.
When external memory access is required, the
physical address is calculated by the Memory
Management Unit and then passed to the Bus
Interface
Unit,
which
between the external system board and the pro-
cessor’s internal execution and cache units.
The
decoupled
single-cycle
instruction
provides
the
interface
Figure 1.1. Integer-Unit Pipeline
1.2 INTEGER UNIT
The superpipelined Integer Unit fetches, decodes,
and executes x86 instructions through the use of a
6-stage integer pipeline (Figure 1.1.).
1.2.1 Pipeline Stages
The
Instruction Fetch
pipe stage generates from
the on-chip cache, a continuous, high-speed
instruction stream for use by the processor. Up to
128 bits of code are read during a single clock
cycle.
Branch prediction logic, within the prefetch unit,
generates a predicted target address for uncondi-
tional or conditional branch instructions. When a
branch instruction is detected, the instruction fetch
stage starts loading instructions at the predicted
address within a single clock cycle. Up to 48 bytes
of code are queued prior to the Instruction Decode
stage.
The
Instruction Decode
stage evaluates the code
stream provided by the instruction fetch stage and
determines the number of bytes in each instruction
and the instruction type. Instructions are pro-
cessed and decoded at a maximum rate of one
instruction per clock.
The
Address Calculation
function is superpipe-
lined and contains two stages, AC1 and AC2. If
the instruction refers to a memory operand, the
AC1 calculates a linear memory address for the
instruction.
The AC2 stage performs any required memory
management functions, cache accesses and reg-
Instruction Fetch Stage
Instruction Decode Stage
Address Calculation Stage 1
Address Calculation Stage 2
Execution Stage
Write Back
1741400
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