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参数资料
| 型号： | ST5x86 |
| 厂商： | 意法半导体 |
| 英文描述： | 100 and 120 MHz 3.45 Volt 5x86 CPU(微处理器) |
| 中文描述： | 100和120兆赫3.45伏特5x86的CPU（微处理器） |
| 文件页数： | 3/39页 |
| 文件大小： | 326K |
| 代理商： | ST5X86 |
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ST5x86
3/39
ister file accesses. If a floating point instruction is
detected by AC2, the instruction is sent to the
floating point unit for processing.
The
Execution
stage, under control of microcode,
executes instructions using the operands provided
by the address calculation stage.
Write-Back,
the last stage of the integer unit,
updates the register file within the integer unit or
writes to the load/store unit within the memory
management unit.
1.2.2 Branch Control
Branch instructions occur, on average, every five
instructions in x86-compatible programs. When
the normal sequential flow of a program changes
due to a branch instruction, the pipeline stages
may stall because they are waiting for the CPU to
calculate or retrieve and decode the new instruc-
tion stream. The 5x86 CPU minimizes the perfor-
mance impact and latency of branch instructions
by using branch prediction.
1.2.3 Branch Prediction
The 5x86 CPU uses a Branch Target Buffer (BTB)
to store branch target addresses and branch pre-
diction information. During the fetch stage, the
instruction stream is checked for the presence of
branch instructions. If an unconditional branch
instruction is encountered, the 5x86 processor
accesses the BTB to check for the branch instruc-
tion’s target address. If the branch instruction hits
in the BTB, the 5x86 CPU begins fetching at the
target address specified by the BTB.
In the case of conditional branches, the BTB also
provides history information to indicate whether
the branch is more likely to be taken or not taken.
If the conditional branch instruction hits in theBTB,
the 5x86 CPU begins fetching instructions at the
predicted target address. The decision to fetch the
taken or not taken target address is based on a
four-state
branch
prediction
achieves approximately 80% prediction accuracy.
If the conditional branch misses in the BTB, the
5x86 processor predicts whether the branch will
be taken or not-taken based on the opcode of the
instruction.
Once fetched, a conditional branch instruction is
decoded and then dispatched to the pipeline. The
conditional branch instruction continues through
the pipeline and is resolved in the EX stage.
Correctly predicted branch instructions execute in
a single clock. If resolution of a branch indicates
that a misprediction has occurred, the 5x86 CPU
flushes the pipeline and starts fetching from the
correct target address. Although the branch is
resolvedin the EX stage, the misprediction latency
is five clock cycles. If a conditional branch misses
inthe BTB, the 5x86 CPU prefetches both the pre-
dicted path and the non-predicted path for each
algorithm
that
conditional branch, eliminating the cache access
cycle on a misprediction.
Since the target address of a return (RET) instruc-
tion is dynamic rather than static, the 5x86 proces-
sor
caches
the
target
instructions in a return stack rather than in the
BTB. The return address is pushed on the return
stack during a CALL instructionand popped during
the corresponding RET instruction.
1.3 Write-Back Cache
The 16-KByte write-back unified cache is a
data/instruction
cache
four-way set associative. The cache stores up to
16 KBytes of code and data in 1024 cache lines.
1.4 Memory Management Unit
The memory management unit translates the lin-
ear address supplied by the integer unit into a
physical address to be used by the cache unit and
the bus interface. Memory management proce-
dures are x86-compatible, adhering to standard
paging mechanisms.
The memory management unit also contains a
load/store unit that is responsible for scheduling
cache
and
external
memory
load/store
unit
incorporates
mance-enhancing features:
Load Store reordering
- prioritizes memory reads required by the
integer unit over writes to external memory
Memory-read bypassing
- eliminates unnecessary memory reads by
using valid data stillin the execution unit.
1.5 Floating Point Unit
The 5x86 processorfloating point unit interfaces to
the integer unit and the cache unit through a 64-bit
bus. The 5x86 CPU FPU is x87-instruction-set
compatible and adheres to the IEEE-754 standard.
Because most applications contain FPU instruc-
tions mixed with integer instructions, the 5x86 FPU
achieves high performance by completing integer
and FPU operations in parallel.
FPU instructions are dispatched to the pipeline
within the integer unit. The address calculation
stage of the pipeline checks for memory manage-
ment exceptions and accesses memory operands
for use by the FPU. Once the instructions and
operands have been provided to the FPU, theFPU
completes instruction execution independently of
the integer unit.
addresses
for
RET
and
is
configured
as
accesses.
two
The
perfor-
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