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| 型号： | ST5x86 |
| 厂商： | 意法半导体 |
| 英文描述： | 100 and 120 MHz 3.45 Volt 5x86 CPU(微处理器) |
| 中文描述： | 100和120兆赫3.45伏特5x86的CPU（微处理器） |
| 文件页数： | 4/39页 |
| 文件大小： | 326K |
| 代理商： | ST5X86 |
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ST5x86
4/39
1.6 Bus Interface Unit
The Bus Interface Unit provides the signals and
timing required by external circuitry. The signal
descriptions and bus interface timing information is
provided in Chapter 3 and Chapter 4 of the data
book.
1.7 Configuration Registers
The 5x86 CPU provides four 8-bit Configuration
Control Registers (CCR1, CCR2, CCR3 and
CCR4)
that
include
control
write-back cache, and SMM features. The CPU
also provides a Power Management Control Reg-
ister (PMR), two 8-bit internal read-only device
identification registers (DIR0 and DIR1), one 24-bit
SMM Address Region Register (SMAR), and an 8
bit Performance Control Register PCR0. The CCR,
PMR, DIR, PCR0, and SMAR registers exist in I/O
memory space and are selected by a “register
index” number as listed inTable 1.1. (Page 5).
Access to these registers is achieved by writing the
index of the register to I/O port 22h. I/O port 23h is
then used for data transfer. Each I/O port 23h data
transfer must be preceded by an I/O port 22h reg-
ister index selection, otherwise the second and
later I/O port 23h operations are directed off-chip
and produce external I/O cycles. If the register
index number is outside the C0h-CFh, FEh-FFh
range, external I/O cycles will also occur.
If the MAPEN field in CCR3 is set to 0001, then
access can be made to the CCR4, PCR0, and
PMR registers. Otherwise, external I/O cycles will
occur if the register index number is outside the
range C0-CFh, FEh, FFh. The MAPEN field must
remain 0 during normal operation to allow system
registers located at port 22h to be accessed.
for
the
on-chip
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