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参数资料
| 型号： | ST72E734J6D0 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42 |
| 封装： | CERAMIC, SDIP-42 |
| 文件页数： | 133/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72E734J6D0 |
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IC SINGLE MASTER BUS INTERFACE (Cont’d)
4.7.4 Functional Description (Master Mode)
Refer to the CR, SR1 and SR2 registers in Section
4.7.5. for the bit definitions.
By default the I2C interface operates in idle mode
(M/IDL bit is cleared) except when it initiates a
transmit or receive sequence.
To switch from default idle mode to Master mode a
Start condition generation is needed.
Start condition and Transmit Slave address
Setting the START bit causes the interface to
switch to Master mode (M/IDL bit set) and
generates a Start condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1
register followed by a write in the DR register with
the Slave address byte, holding the SCL line low
(see Figure 54 Transfer sequencing EV1).
Then the slave address byte is sent to the SDA line
via the internal shift register.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1
register followed by a write in the CR register (for
example set PE bit), holding the SCL line low
(see Figure 54 Transfer sequencing EV2).
Next
the
master
must
enter
Receiver
or
Transmitter mode.
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR
register via the internal shift register. After each
byte the interface generates in sequence:
– Acknowledge pulse if if the ACK bit is set
– EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Then the interface waits for a read of the SR1
register followed by a read of the DR register,
holding the SCL line low (see Figure 54 Transfer
sequencing EV3).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to idle mode (M/IDL bit
cleared).
Note: In order to generate the non-acknowledge pulse af-
ter the last received data byte, the ACK bit must be
cleared just before reading the second last data
byte.
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the internal
shift register.
The master waits for a read of the SR1 register
followed by a write in the DR register, holding the
SCL line low (see Figure 54 Transfer sequencing
EV4).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to idle mode (M/IDL bit
cleared).
Error Case
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
Note: The SCL line is not held low.
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