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参数资料
| 型号： | ST72E734J6D0 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42 |
| 封装： | CERAMIC, SDIP-42 |
| 文件页数： | 8/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72E734J6D0 |
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ST72774/ST727754/ST72734
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DDC INTERFACE (Cont’d)
s
Write Operation
Once the DDC1/2B Interface has acknowledged a
write transfer request, i.e. a Device Address with
RW=0, it waits for a data address. When the latter
is received, it is acknowledged and loaded into the
ALR.
Then, the master may send any number of data
bytes that are all acknowledged by the DDC1/2B
Interface. The data bytes are written in RAM if the
WP bit=0 in the DCR register, otherwise the RAM
location is not modified.
In any case, all write operations are performed
in RAM and therefore do not delay DDC
transfers,
although
concurrent
software
execution is halted for 2 cycles.
After each byte is transferred, the internal address
counter is automatically incremented.
If the counter is pointing to the top of the structure,
it rolls over to the bottom since the incrementation
is performed only on the 7 or 8 LSB’s of the pointer
depending on the selected data structure size. In
other words, ALR rolls over from FFh to 00h for
Device
Addresses
A2h/A3h
and
A6h/A7h.
Otherwise, it rolls over from 7Fh to 00h or from FFh
to 80h depending on the MSB of the last data
address received.
Then after that last byte has been effectively
written in RAM, the EDF flag is set and an interrupt
is generated if EDE is set.
The
transfer
is
terminated
by
the
master
generating a STOP condition.
Figure 65. Write sequence
s
Read Operations
All read operations consist of retrieving the data
pointed to by an internal address counter which is
initialized by a dummy write and incremented by
any read. The DDC1/2B Interface always waits for
an acknowledge during the 9th bit-time. If the
master does not pull the SDA line low during this
bit-time, the DDC1/2B Interface ends the transfer
and switches to a stand-by state.
– Current address read: After generating a
START condition the master sends a read device
address (RW = 1). The DDC1/2B Interface ac-
knowledges this and outputs the data byte point-
ed to by the internal address pointer which is
subsequently incremented. The master must
NOT acknowledge this byte and must terminate
the transfer with a STOP condition.
– Random address read: The master performs a
dummy write to load the data address into the
ALR. Then the master sends a RESTART condi-
tion followed by a read Device Address (RW=1).
– Sequential address read: This mode is similar
to the current and random address reads, except
that the master DOES acknowledge the data
byte for the DDC1/2B Interface to output the next
byte in sequence. To terminate the read opera-
tion the master must NOT acknowledge the last
data byte and must generate a STOP condition.
The data output are from consecutive memory
addresses. The internal address counter is incre-
mented automatically after each byte. If the
counter is pointing to the top of the structure, it
rolls over to the bottom since the incrementation
is performed only on the 7 or 8 LSB’s of the
counter depending on the selected data structure
size.
STAR
T
R/W
AC
K
DATA ADDR.
DATA IN 1
DATA IN 2
AC
K
AC
K
DATA IN n
AC
K
STOP
AC
K
DEV ADDR
SDA
XXXXh
ADDR
ADDR + n -1
Addr.
Pointer
ADDR + 1
ADDR + n
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