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参数资料
型号： ST72E734J6D0
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42
封装： CERAMIC, SDIP-42
文件页数： 74/144页
文件大小： 1280K
代理商： ST72E734J6D0
ST72774/ST727754/ST72734
35/144
I/O PORTS (Cont’d)
4.1.6 Port D
The Port D I/O pins are normally used for the input
and output of video synchronization signals of the
Sync Processor, but are set to I/O Input with pull-
up upon reset. The I/O mode can be set
individually for each port bit to Input with pull-up
and output push-pull through the Port D DDR.
The configuration to support the Sync Processor
requires that the SYNOP (bit7) and CLMPEN (bit6)
of the ENR (Enable Register of SYNC) is reset.
SYNOP enables port D bits 0,1 and CLMPEN
enables Port D bit 6 to the sync outputs.
Port D, bit 4:3 are the alternate inputs ITA, ITB, (for
the interrupt falling edge detector).
When a falling edge occurs on these inputs, an
interrupt will be generated depending on the status
of the INTX (ITAITE & ITBITE) bits in the MISCR
Register.
Port D, bit 6 is switched to the alternate
(CLAMPOUT) by resetting the CLMPEN bit of the
ENR Register inside SYNC block.
If the SYNC function is selected, Port D bit 5 and 3
MUST be set as input to enable the HFBACK or
VFBACK timing inputs.
Note: As these inputs are switched from normal
I/O functionality, the video synchronization signals
may also be monitored directly through the Port D
Data Register for such tasks as checking for the
presence of video signals or checking the polarity of
Horizontal and Vertical synchronization signals
(when the Sync Inputs are switched directly to the
outputs using the multiplexers of the Sync Proces-
sor).
Table 11. Port D Description
PORT D
I / O
Alternate Function
Input*
Output
Signal
Condition
PD0
With pull-up
Push-pull
VSYNCO
(push pull output)
SYNOP=0
(ENR [SYNC])
PD1
With pull-up
Push-pull
HSYNCO
(push pull output)
SYNOP=0
(ENR [SYNC])
PD2
With pull-up
Push-pull
CSYNCI (input with TTL Schmitt
trigger & pull-up)
-
PD3
With pull-up
Push-pull
ITA (input with CMOS Schmitt
trigger & pull-up)
-
VFBACK (input with TTL Schmitt
trigger & pull-up)
-
PD4
With pull-up
Push-pull
ITB (input with CMOS Schmitt
trigger & pull-up)
-
PD5
With pull-up
Push-pull
HFBACK (input with TTL Schmitt
trigger & pull-up)
-
PD6
With pull-up
Push-pull
CLAMPOUT
(push pull output)
CLMPEN=0
(ENR [SYNC])
* Reset state
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