收藏本站
参数资料
型号： ST72F60E1M1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封装： 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件页数： 121/139页
文件大小： 1993K
代理商： ST72F60E1M1
Serial communications interface (SCI)
ST7260xx
82/139
13.3
Register description
13.3.1
Status register (SCISR)
SCISR
Reset value:
1100 0000 (C0h)
76
543
21
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PE
R
RRR
RR
Table 38.
SCISR register description
Bit
Name
Function
7
TDRE
Transmit Data Register Empty
This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a write to the SCIDR register).
0: Data is not transferred to the shift register.
1: Data is transferred to the shift register.
Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.
6TC
Transmission Complete
This bit is set by hardware when transmission of a frame containing data is complete.
An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a Preamble or a Break.
5
RDRF
Received Data Ready Flag
This bit is set by hardware when the content of the RDR register has been
transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
4IDLE
Idle line detect
This bit is set by hardware when a Idle Line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a read to the SCIDR register).
0: No idle line is detected
1: Idle line is detected
Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new
idle line occurs).
相关PDF资料
PDF描述
ST72F60K2DIE1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, UUC
ST72F60K2DIE6 8-BIT, MROM, 8 MHz, MICROCONTROLLER, UUC
ST72F651AR6T1 8-BIT, FLASH, MICROCONTROLLER, PQFP64
ST72P60E2M1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
ST7260E2M1/XXX 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
相关代理商/技术参数
参数描述
ST72F60E2M1 功能描述:8位微控制器 -MCU ST7262 Lo Spd USB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F60K1U1 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F60K1U1TR 功能描述:8位微控制器 -MCU ST7262 Lo Spd USB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F60K2B1 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F60K2U1TR 功能描述:8位微控制器 -MCU ST7262 Lo Spd USB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*