参数资料
型号: ST72F60E1M1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封装: 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件页数: 41/139页
文件大小: 1993K
代理商: ST72F60E1M1
ST7260xx
Known limitations
135/139
19
Known limitations
19.1
PA2 limitation with OCMP1 enabled
Description
This limitation affects only Rev B Flash devices (with Internal Sales Type 72F60xxxxx$x7); it
has been corrected in Rev W Flash devices (with Internal Sales Type 72F60xxxxx$x9).
When Output Compare 1 function (OCMP1) on pin PA6 is enabled by setting the OC1E bit in
the TCR2 register, pin PA2 is also affected.
In particular, the PA2 pin is forced to be floating even if port configuration (PADDR+PADR)
has set it as output low. However, it can be still used as an input.
19.2
Unexpected reset fetch
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt
controller does not recognise the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.
19.3
SCI wrong break duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
20 bits instead of 10 bits if M=0
22 bits instead of 11 bits if M=1
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generate one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (fCPU=8 MHz and SCIBRR=0xC9), the wrong break duration
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
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