参数资料
型号: ST72F60E1M1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封装: 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件页数: 99/139页
文件大小: 1993K
代理商: ST72F60E1M1
Watchdog timer (WDG)
ST7260xx
62/139
12.4.4
Low power modes
12.4.5
Interrupts
Table 28.
Effect of low power modes on 16-bit timer
Mode
Description
Wait
No effect on 16-bit timer.
Timer interrupts cause the device to exit from Wait mode.
Halt
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes
from the previous count when the MCU is woken up by an interrupt with Exit from Halt
mode capability or from the counter reset value when the MCU is woken up by a reset.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with Exit from Halt
mode capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
Table 29.
16-bit timer interrupt control/wake-up capability(1)
1.
The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 8: Interrupts).
These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Interrupt event
Event flag Enable control bit
Exit from Wait
Exit from Halt
Input Capture 1 event/counter
reset in PWM mode
ICF1
ICIE
Yes
No
Input Capture 2 event
ICF2
Output Compare 1 event
(not available in PWM mode)
OCF1
OCIE
Output Compare 2 event
(not available in PWM mode)
OCF2
Timer Overflow event
TOF
TOIE
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