参数资料
型号: ST72F60E1M1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封装: 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件页数: 135/139页
文件大小: 1993K
代理商: ST72F60E1M1
ST7260xx
USB interface (USB)
95/139
14.4.7
Device address register (DADDR)
Bit 7 = Reserved. Forced by hardware to 0.
Bits 6:0 = ADD[6:0] Device address, 7 bits.
Software must write into this register the address sent by the host during enumeration.
Note:
This register is also reset when a USB reset is received from the USB bus or forced through
bit FRES in the CTLR register.
14.4.8
Endpoint n register A (EPnRA)
These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission.
They are also reset by the USB bus reset.
Note:
Endpoint 2 and the EP2RA register are not available on some devices (see device feature
list and register map).
Bit 7 = ST_OUT Status out.
This bit is set by software to indicate that a status out packet is expected: in this case, all
nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed. When
ST_OUT is reset, OUT transactions can have any number of bytes, as needed.
Bit 6 = DTOG_TX Data Toggle, for transmission transfers.
It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles
only when the transmitter has received the ACK signal from the USB host. DTOG_TX and
also DTOG_RX (see EPnRB) are normally updated by hardware, at the receipt of a relevant
PID. They can be also written by software.
Bits 5:4 = STAT_TX[1:0] Status bits, for transmission transfers.
These bits contain the information about the endpoint status, which are listed below:
DADDR
Reset value:
0000 0000 (00h)
76
543
21
0
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
R/W
EPnRA
Reset value:
0000 xxxx (0xh)
76
543
21
0
ST_
OUT
DTOG
_TX
STAT
_TX1
STAT
_TX0
TBC3
TBC2
TBC1
TBC0
R/W
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