参数资料
型号: ST72F60E1M1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
封装: 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件页数: 64/139页
文件大小: 1993K
代理商: ST72F60E1M1
Interrupts
ST7260xx
30/139
8
Interrupts
The ST7 core may be interrupted by one of two different methods: maskable hardware
interrupts as listed in Table 10: Interrupt mapping and a non-maskable software interrupt
(TRAP). The Interrupt processing flowchart is shown in Figure 16.
The maskable interrupts must be enabled clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed when they are enabled (see external
interrupts subsection).
When an interrupt has to be serviced:
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
The I bit of the CC register is set to prevent additional interrupts.
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 10: Interrupt mapping for
vector addresses).
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
As a consequence of the IRET instruction, the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case several interrupts are simultaneously pending, a hardware priority defines which
one will be serviced first (see Table 10: Interrupt mapping).
Non-maskable software interrupts
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It will be serviced according to the flowchart on Figure 16.
Interrupts and low power mode
All interrupts allow the processor to leave the Wait low power mode. Only external and
specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to
the “Exit from HALT“ column in Table 10: Interrupt mapping).
External interrupts
The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising
edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7)
can generate an interrupt when a falling edge occurs on this pin.
Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE
register and if the I bit of the CCR is reset.
相关PDF资料
PDF描述
ST72F60K2DIE1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, UUC
ST72F60K2DIE6 8-BIT, MROM, 8 MHz, MICROCONTROLLER, UUC
ST72F651AR6T1 8-BIT, FLASH, MICROCONTROLLER, PQFP64
ST72P60E2M1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
ST7260E2M1/XXX 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
相关代理商/技术参数
参数描述
ST72F60E2M1 功能描述:8位微控制器 -MCU ST7262 Lo Spd USB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F60K1U1 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F60K1U1TR 功能描述:8位微控制器 -MCU ST7262 Lo Spd USB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F60K2B1 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F60K2U1TR 功能描述:8位微控制器 -MCU ST7262 Lo Spd USB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT