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ST72774/ST727754/ST72734
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TIMING MEASUREMENT UNIT (Cont’d)
4.5.4 Register Description
CONTROL STATUS REGISTER (TMUCSR)
Bit 7:2 - Read only
Bit 1:0 - Read/Write
Reset Value: 1111 1100 (FCh)
Bit 7:5 = T2[10:8]
MSB of T2 Counter.
Most Significant Bits of the T2 counter value (see
T2 Counter register description).
Bit 4:2= T1[10:8]
MSB T1 Counter.
Most Significant Bits of the T1 counter value (see
T1 Counter register description).
Bit 1 = H_V
Horizontal or Vertical Measurement.
This bit is set and cleared by software to select the
type of measurement. It cannot be modified while
the START bit = 1 (measurement in progress).
0: Vertical measurement.
1: Horizontal measurement.
Bit 0 = START
Start measurement.
This bit is set by software and cleared by hardware
when the measurements are completed. It can not
be cleared by software.
0: Measurement done.
1: Start measurement.
T1 COUNTER REGISTER (TMUT1CR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the low part of
the counter value.
When a T1 measurement is finished (rising edge
on AV input), the 11-bit counter value is transferred
to this register and to the T1[10:8] bits in the CSR
register.
T1 is H1 value if the H_V bit = 1.
T1 is V1 value if the H_V bit = 0.
T2 COUNTER REGISTER (TMUT2CR)
Read Only
Reset Value: 1111 1111(FFh)
This is an 8-bit register that contains the low part of
the counter value.
When a T2 measurement is finished (rising edge
on the selected sync signal), the 11-bit counter
value is transferred to this register and to the
T2[10:8] bits in the CSR register.
T2 is H2 value if the H_V bit = 1.
T2 is V2 value if the H_V bit = 0.
70
T2[10] T2[9] T2[8] T1[10] T1[9] T1[8]
H_V START
70
T1[7]
T1[0]
70
T2[7]
T2[0]