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SYNC PROCESSOR (SYNC) (Cont’d)
4.4.3 Input Signals
The Sync Processor has the following inputs (TTL
level):
– VSYNCI1 Vertical Sync input1
– HSYNCI1 Horizontal Sync input1 or Composite
sync
– VSYNCI2 Vertical Sync input2
– HSYNCI2 Horizontal Sync input2 or Composite
sync
Note: The above input pairs can be used for DSUB or
BNC connectors. To select these inputs use the
HVSEL bit in the POLR register.
– CSYNCI Sync on Green (external extractor)
Note: If the CSYNCI pin is needed for another I/O func-
tion, the composite sync signal can be connected to
HSYNCI using the SCI0 bit in the MCR register.
– HFBACK Horizontal Flyback input
– VFBACK Vertical Flyback input
4.4.4 Input Signal Waveforms
– The input signals must contain only synchroniza-
tion pulses. In case of serration pulses on CSYN-
CI/HSYNCI, the pulse width should be less than
8s.
– The VSYNCI signal is internally connected to
Timer Input Capture 1 (ICAP1).
– The HSYNCI or CSYNCI signal, prescaled by
256, is internally connected to Timer Input Cap-
ture 2 (ICAP2).
– Typical timing range: See Figure 38 and 39
– If the timer clock is 2 MHz (external oscillator fre-
quency 24 MHz):
PV accuracy = +/- 1 Timer clock (500ns)
PH*256 accuracy = +/- 1 Timer clock (500ns)
(PV= Vertical pulse, PH = Horizontal pulse)
4.4.5 Output Signals
The Sync Processor has the following outputs:
HSYNCO Horizontal Sync Output
Enable: SYNOP bit in ENR register
Programmable polarity:
HS0/HS1 bits in MCR register
In case of composite sync signal, the signal can be
blanked by software during the vertical period
(HINH bit in ENR register).
In case of separate sync, no blanking is generated.
VSYNCO Vertical Sync Output
Enable: SYNOP bit in ENR register
Programmable polarity:
VOP bit in the MCR register
In case of composite sync the delay of the
extracted Vsync signal is:
minimum: 500ns + HSYNCO pulse width
maximum: 8750ns (max. threshold in ex-
traction mode)