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参数资料
| 型号： | ST7PLU05MAE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 30/124页 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU05MAE |
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ST7LUS5, ST7LU05, ST7LU09
Package pinout and device pin description
13/124
Table 2.
Device pin description(1)
1.
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Pin
Ty
p
e
(2)
2.
Type: I = input, O = output, S = supply
Level
Port / Control
Function
No.
Name
In
pu
t(3
)
3.
In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger
Ou
tpu
t(4)
4.
Output level: HS = High sink (on N-buffer only)
Input(5)
5.
Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
Output(6)
6.
Output: OD = open drain, PP = push-pull
Main
(after
reset)
Alternate
float
wp
u
int
ana
OD
PP
1VDD
(7)
7.
It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
S
Main power supply
2
PA5/AIN4/CLKIN
I/O CT HS X
ei4
X
Port A5
Analog input 4 or External Clock
Input
3
PA4/AIN3
I/O CT HS X
ei3
X
Port A4 Analog input 3
4
PA3/RESET(8)
8.
After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to
MUXCR0 and AAh to MUXCR1. For further details, please refer to Section 6.4: Register description on page 36.
O
X
XX
Port A3 RESET(8)
5
PA2/AIN2/LTIC
I/O CT HS X
ei2
X
Port A2
Analog input 2 or Lite Timer
Input Capture
6
PA1/AIN1/ICCCLK
I/O CT HS X
ei1
X
Port A1
Analog input 1 or In-Circuit
Communication Clock
Caution: During normal
operation this pin must be
pulled-up, internally or externally
(external pull-up of 10k
mandatory in noisy
environment).
7
PA0/AIN0/ATPWM/ICCDATA I/O CT HS X
ei0
X
Port A0
Analog input 0 or Auto-Reload
Timer PWM or In-Circuit
Communication Data
8VSS
S
Ground
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