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参数资料
| 型号： | ST7PLU05MAE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 61/124页 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU05MAE |
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ST7LUS5, ST7LU05, ST7LU09
Interrupts
41/124
7.4
System integrity management (SI)
The System Integrity Management block contains the low voltage detector (LVD) function. It
is managed by the SICSR register.
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Illegal opcode reset on page 87 for further details.
7.4.1
Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
as the power-down keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when VDD is below:
●
VIT+(LVD) when VDD is rising
●
VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 14.
The high voltage threshold can be activated by option byte. See Section 14.1 on page 114.
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),
the MCU can only be in two modes:
●
under full software control
●
in static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
Note:
Use of LVD with capacitive power supply: If power cuts occur in the application with this type
of power supply, it is recommended to pull VDD down to 0V to ensure optimum restart
conditions. Refer to circuit example in Figure 57 on page 109 and note 4.
The LVD is an optional function which can be selected by option byte (see Section 14.1 on
page 114). It allows the device to be used without any external RESET circuitry. If the LVD is
disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from Reset, to ensure the application functions properly.
Caution:
If an LVD reset occurs after a watchdog reset has occurred, the LVD takes priority and
clears the watchdog flag.
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