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参数资料
| 型号： | ST7PLU05MAE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 97/124页 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU05MAE |
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On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
PWM0 control/status register (PWM0CSR)
PWM output control register (PWMCR)
11:0
DCR[11:0]
PWMx Duty Cycle Value
This 12-bit value is written by software. The high register must be written first.
In PWM mode (OE0 = 1 in the PWMCR register) the DCR[11:0] bits define the
duty cycle of the PWM0 output signal (see Figure 32). In Output Compare
mode, (OE0 = 0 in the PWMCR register) they define the value to be compared
with the 12-bit up counter value.
PWM0CSR
Reset value: 0000 0000 (00h)
7
654
32
10
Reserved
OP0
CMPF0
-R/W
R/W
Table 44.
PWM0CSR register description
Bit
Name
Function
7:2
-
Reserved, must be kept cleared.
1OP0
PWM0 Output Polarity
This bit is read/write by software and cleared by hardware after a reset. This bit
selects the polarity of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
0CMPF0
PWM0 Compare Flag
This bit is set by hardware and cleared by software by reading the PWM0CSR
register. It indicates that the up counter value matches the DCR0 register value.
0: Up counter value does not match DCR value
1: Up counter value matches DCR value
PWMCR
Reset value: 0000 0000 (00h)
7
654
32
10
Reserved
OE0
-R/W
Table 45.
PWMCR register description
Bit
Name
Function
7:1
-
Reserved, must be kept cleared.
0OE0
PWM0 Output enable.
This bit is set and cleared by software.
0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O)
1: PWM0 output enabled
Table 43.
DCR0 high and low register descriptions (continued)
Bits
Name
Function
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