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| 型号： | ST7PLU05MAE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 6/124页 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU05MAE |
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ST7LUS5, ST7LU05, ST7LU09
Electrical characteristics
103/124
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
●
DLU: Electrostatic discharges (one positive then one negative test) are applied to each
pin of three samples when the micro is running to assess the latch-up performance in
dynamic mode. Power supplies are set to the typical values, the oscillator is connected
as near as possible to the pins of the micro and the component is put in reset mode.
This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details,
refer to the application note AN1181.
12.8
I/O port pin characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Table 78.
Electrical sensitivities
Symbol
Parameter
Conditions
Class(1)
1.
Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, meaning that when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
LU
Static latch-up class
TA = +125°C
A
DLU
Dynamic latch-up class
VDD = 5.5V, fOSC = 4 MHz, TA = +25°C
A
Table 79.
General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
-40°C to 125°C
0.3VDD
V
VIH
Input high level voltage
0.7VDD
Vhys
Schmitt trigger voltage
hysteresis(1)
1.
Data based on characterization results, not tested in production
400
mV
IL
Input leakage current
VSS < VIN < VDD
±1
A
IS
Static current consumption
induced by each floating
input pin(2)
2.
Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of
the I/O for example or an external pull-up or pull-down resistor (see Figure 48). Static peak current value
taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in
production. This value depends on VDD and temperature values.
Floating input mode
400
RPU
Weak pull-up equivalent
resistor(3)(4)
VIN =VSS
VDD = 5V
80
120
170
k
VDD = 3.3V
CIO
I/O pin capacitance
5
pF
tf(IO)out
Output high to low level fall
CL = 50 pF
Between 10% and 90%
25
ns
tr(IO)out
Output low to high level rise
25
tw(IT)in
External interrupt pulse
time(5)
1tCPU
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