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参数资料
| 型号： | ST7PLU05MAE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 94/124页 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU05MAE |
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ST7LUS5, ST7LU05, ST7LU09
On-chip peripherals
71/124
10.2.5
Interrupts
10.2.6
Register description
Timer control status register (ATCSR)
Table 39.
AT timer interrupt control/wake-up capability
Interrupt event(1)
1.
The interrupt events are connected to separate interrupt vectors (see Chapter 7: Interrupts).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC
register is reset (RIM instruction).
Event flag
Enable control
bit
Exit from
Wait
Exit from
Halt
Exit from
Active Halt
Overflow event
OVF
OVFIE
Yes
No
Yes(2)
2.
Only if CK0 = 1 and CK1 = 0.
CMP event
CMPFx
CMPIE
No
ATCSR
Reset value: 0000 0000 (00h)
7
654
32
10
Reserved
CK[1:0]
OVF
OVFIE
CMPIE
-
R/W
Table 40.
ATCSR register description
Bit
Name
Function
7:5
-
Reserved, must be kept cleared.
4:3
CK[1:0]
Counter Clock Selection
These bits are set and cleared by software and cleared by hardware after a reset.
They select the clock frequency of the counter.
00: Off
01: fLTIMER (1ms timebase @ 8 MHz)
10: fCPU
11: Reserved
2OVF
Overflow Flag
This bit is set by hardware and cleared by software by reading the ATCSR
register. It indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
Caution: When set, the OVF bit stays high for 1 fCOUNTER cycle (up to 1ms
depending on the clock selection) after it has been cleared by software.
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