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参数资料
| 型号： | ST7PLU05MAE |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 68/124页 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU05MAE |
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Power saving modes
ST7LUS5, ST7LU05, ST7LU09
Figure 20.
Active Halt mode flowchart
1.
Peripherals clocked with an external clock source can still be active.
2.
Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from Active Halt mode.
3.
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
8.4.2
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when active halt mode is disabled.
The MCU can exit Halt mode on reception of either a specific interrupt (see Table 15:
Interrupt mapping on page 39) or a RESET. When exiting Halt mode by means of a RESET
or an interrupt, the main oscillator is immediately turned on and the 64 CPU cycle delay is
used to stabilize it. After the start up delay, the CPU resumes operation by servicing the
interrupt or by fetching the reset vector which woke it up (see Figure 22).
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
HALT INSTRUCTION
RESET
INTERRUPT(2)
Y
N
Y
CPU
OSCILLATOR
PERIPHERALS(1)
IBIT
ON
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS(1)
IBIT
ON
OFF
X(3)
ON
CPU
OSCILLATOR
PERIPHERALS
IBITS
ON
X(3)
ON
64 CPU CLOCK CYCLE
DELAY
(Active Halt enabled)
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