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参数资料
| 型号： | STPCC0175BTI3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 75 MHz, MICROPROCESSOR, PBGA388 |
| 封装： | PLASTIC, BGA-388 |
| 文件页数： | 10/47页 |
| 文件大小： | 747K |
| 代理商： | STPCC0175BTI3 |
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PIN DESCRIPTION
18/47
Issue 1.6
PCI_CLKO
33MHz PCI Output Clock.
This is the master PCI bus clock output.
AD[31:0]
PCI Address/Data. This is the
32-bit PCI multiplexed address and data
bus. This bus is driven by the master
during the address phase and data
phase of write transactions. It is driven by
the target during data phase of read
transactions.
CBE#[3:0]
Bus
Commands/Byte
Enables. These are the multiplexed
command and Byte enable signals of the
PCI bus. During the address phase they
define the command and during the data
phase
they
carry
the
Byte
enable
information. These pins are inputs when
a PCI master other than the STPC Client
owns the bus and outputs when the
STPC Client owns the bus.
FRAME#
Cycle Frame. This is the frame
signal of the PCI bus. It is an input when
a PCI master owns the bus and is an
output when STPC Client owns the PCI
bus.
TRDY#
Target Ready. This is the target
ready signal of the PCI bus. It is driven as
an output when the STPC Client is the
target of the current bus transaction. It is
used as an input when STPC Client
initiates a cycle on the PCI bus.
IRDY#
Initiator Ready. This is the initiator
ready signal of the PCI bus. It is used as
an output when the STPC Client initiates
a bus cycle on the PCI bus. It is used as
an input during the PCI cycles targeted to
the STPC Client to determine when the
current PCI master is ready to complete
the current transaction.
STOP#
Stop Transaction. Stop is used to
implement the disconnect, retry and
abort protocol of the PCI bus. It is used
as an input for the bus cycles initiated by
the STPC Client and is used as an output
when a PCI master cycle is targeted to
the STPC Client.
DEVSEL#
I/O Device Select. This signal
is used as an input when the STPC Client
initiates a bus cycle on the PCI bus to
determine if a PCI slave device has
decoded itself to be the target of the
current transaction. It is asserted as an
output either when the STPC Client is the
target of the current PCI transaction or
when no other device asserts DEVSEL#
prior to the subtractive decode phase of
the current PCI transaction.
PAR
Parity Signal Transactions. This is
the parity signal of the PCI bus. This
signal is used to guarantee even parity
across AD[31:0], CBE#[3:0], and PAR.
This signal is driven by the master during
the address phase and data phase of
write transactions. It is driven by the
target
during
data
phase
of
read
transactions. (Its assertion is identical to
that of the AD bus delayed by one PCI
clock cycle)
SERR#
System Error. This is the system
error signal of the PCI bus. It may, if
enabled, be asserted for one PCI clock
cycle if the target aborts an STPC Client
initiated PCI transaction. Its assertion by
either the STPC Client or by another PCI
bus agent will trigger the assertion of NMI
to the host CPU. This is an open drain
output.
LOCK#
PCI Lock. This is the lock signal
of the PCI bus and is used to implement
the exclusive bus operations when acting
as a PCI target agent.
PCI_REQ#[2:0]
PCI Request. These
pins are the three external PCI master
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