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参数资料
型号： STPCC0175BTI3
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 75 MHz, MICROPROCESSOR, PBGA388
封装： PLASTIC, BGA-388
文件页数： 15/47页
文件大小： 747K
代理商： STPCC0175BTI3
PIN DESCRIPTION
22/47
Issue 1.6
IOR#
I/O Read. This is the IO read
command signal of the ISA bus. It is an
input when an ISA master owns the bus
and is an output at all other times.
IOW#
I/O Write. This is the IO write
command signal of the ISA bus. It is an
input when an ISA master owns the bus
and is an output at all other times.
MASTER#
Add On Card Owns Bus. This
signal is active when an ISA device has
been granted bus ownership.
MCS16#
Memory Chip Select 16. This is
the decode of LA23-17 address pins of
the
ISA
address
bus
without
any
qualification of the command signal lines.
MCS16# is always an input. The STPC
Client ignores this signal during IO and
refresh cycles.
IOCS16#
IO Chip Select16. This signal is
the decode of SA15-0 address pins of the
ISA address bus without any qualification
of the command signals. The STPC
Client does not drive IOCS16# (similar to
PC-AT design). An ISA master access to
an internal register of the STPC Client is
executed as an extended 8-bit IO cycle.
REF#
Refresh Cycle. This is the refresh
command signal of the ISA bus. It is
driven as an output when the STPC
Client performs a refresh cycle on the
ISA bus. It is used as an input when an
ISA master owns the bus and is used to
trigger a refresh cycle.
The STPC Client performs a pseudo
hidden refresh. It requests the host bus
for two host clocks to drive the refresh
address and capture it in external buffers.
The host bus is then relinquished while
the refresh cycle continues on the ISA
bus.
AEN
Address Enable. Address Enable is
enabled when the DMA controller is the
bus owner to indicate that a DMA transfer
will occur. The enabling of the signal
indicates to IO devices to ignore the
IOR#/IOW# signal during DMA transfers.
IOCHCK#
IO
Channel
Check.
IO
Channel Check is enabled by any ISA
device to signal an error condition that
can
not
be
corrected.
NMI
signal
becomes active upon seeing IOCHCK#
active if the corresponding bit in Port B is
enabled.
ISAOE#
Bidirectional OE Control. This
signal controls the OE signal of the
external transceiver that connects the
IDE DD bus and ISA SA bus.
GPIOCS#
I/O General Purpose Chip
Select 1. This output signal is used by the
external latch on ISA bus to latch the data
on the SD[7:0] bus. The latch can be use
by the PMU unit to control the external
peripheral devices to power down or any
other desired function.
This pin is also serves as a strap input
during reset.
3.2.9.
IDE CONTROL
PIRQ
Primary
Interrupt
Request.
Interrupt
request
from
primary
IDE
channel.
SIRQ
Secondary
Interrupt
Request.
Interrupt request from secondary IDE
channel.
PDRQ
Primary DMA Request. DMA
request from primary IDE channel.
SDRQ
Secondary DMA Request. DMA
request from secondary IDE channel.
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