参数资料
型号: STPCC0175BTI3
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 75 MHz, MICROPROCESSOR, PBGA388
封装: PLASTIC, BGA-388
文件页数: 8/47页
文件大小: 747K
代理商: STPCC0175BTI3
PIN DESCRIPTION
16/47
Issue 1.6
3.2.SIGNAL DESCRIPTIONS
3.2.1.
BASIC CLOCKS RESETS & XTAL
PWGD
System Reset/Power good. This
input is low when the the reset switch is
depressed. Otherwise, it reflects the
power
supply’s
power
good
signal.
PWGD is asynchronous to all clocks, and
acts as a negative active reset. The reset
circuit initiates a hard reset on the rising
edge of PWGD.
XTALI
14.3MHz Pull Down (10 kOhm)
XTALO
14.3MHz External
Oscillator
Input These pins are the 14.318 MHz
external oscilator input; This clock is
used as the reference clock for the
internal
frequency
synthesizer
to
generate the HCLK, CLK24M, GCLK2X
and DCLK clocks.
HCLK
Host Clock. This is the host 1X
clock. Its frequency can vary from 25 to
75 MHz. All host transactions and PCI
transactions are synchronized to this
clock. This clock drives the
DRAM
controller
to
execute
the
host
transactions. In normal mode, this output
clock is generated by the internal pll.
GCLK2X
80MHz Graphics Clock. This is
the Graphics 2X clock, which drives the
graphics engine and the the DRAM
controller to execute the graphics and
display cycles.
Normally GCLK2X is generated by the
internal frequency synthesizer, and this
pin is an output. By setting a bit in Strap
Register 2, this pin can be made an input
so that an external clock can replace the
internal frequency synthesizer.
DCLK
135MHz Dot Clock. This is the dot
clock, which drives graphics display
cycles. Its frequency can be as high as
135 MHz, and it is required to have a
worst case duty cycle of 60-40.
This signal is either driven by the internal
pll (VGA) or either by an external 27MHz
oscillator (TV).
DCLK_DIR
Dot
Clock
Direction.
Specifies if DCLK is an input (0) or an
output (1).
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