
PIN DESCRIPTION
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Issue 1.6
3.2.7.
ISA/IDE COMBINED CONTROL
IOCHRDY/DIORDY
Channel
Ready
(ISA)/Busy/Ready (IDE). This is a multi-
function pin. When the ISA bus is active,
this pin is IOCHRDY. When the IDE bus
is active, this serves as IDE signal
DIORDY.
IOCHRDY is the IO channel ready signal
of the ISA bus and is driven as an output
in response to an ISA master cycle
targeted to the host bus or an internal
register of the STPC Client. The STPC
Client monitors this signal as an input
when performing an ISA cycle on behalf
of the host CPU, DMA master or refresh.
ISA masters which do not monitor
IOCHRDY are not guaranteed to work
with the STPC Client since the access to
the system memory can be considerably
delayed due to CRT refresh or a write
back cycle.
3.2.8.
ISA CONTROL
SYSRSTO#
Reset Output to System.
This is the system reset signal and is
used to reset the rest of the components
(not on Host bus) in the system. The ISA
bus reset is
an externally inverted
buffered version of this output and the
PCI bus reset is an externally buffered
version of this output.
ISA_CLK
ISA
Clock
Output
(also
Multiplexer Select Line For IPC). This pin
produces the Clock signal for the ISA
bus. It is also used with ISA_CLK2X as
the multiplexor control lines for the
Interrupt Controller Interrupt input lines.
This is a divided down version of either
the PCICLK or OSC14M.
ISA_CLKX2
ISA Clock Output (also
Multiplexer Select Line For IPC). This pin
produces a signal at twice the frequency
of the Clock signal for the ISA bus. It is
also
used
with
ISA_CLK
as
the
multiplexor control lines for the Interrupt
Controller Interrupt input lines.
OSC14M
ISA bus synchronisation clock
Output. This is the buffered 14.318 Mhz
clock to the ISA bus.
ALE
Address Latch Enable. This is the
address latch enable output of the ISA
bus and is asserted by the STPC Client
to indicate that LA23-17, SA19-0, AEN
and SBHE# signals are valid. The ALE is
driven high during refresh, DMA master
or ISA master cycles by the STPC Client.
ALE is driven low after reset.
BHE#
System Bus High Enable. This
signal, when asserted, indicates that a
data Byte is being transferred on SD15-8
lines. It is used as an input when an ISA
master owns the bus and is an output at
all other times.
MEMR#
Memory Read. This is the
memory read command signal of the ISA
bus. It is used as an input when an ISA
master owns the bus and is an output at
all other times.
The MEMR# signal is active during
refresh.
MEMW#
Memory Write. This is the
memory write command signal of the ISA
bus. It is used as an input when an ISA
master owns the bus and is an output at
all other times.
SMEMR#
System Memory Read. The
STPC Client generates SMEMR# signal
of the ISA bus only when the address is
below 1MByte or the cycle is a refresh
cycle.
SMEMW#
System Memory Write. The
STPC Client generates SMEMW# signal
of the ISA bus only when the address is
below one MByte.