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参数资料
| 型号： | STPCC0175BTI3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 75 MHz, MICROPROCESSOR, PBGA388 |
| 封装： | PLASTIC, BGA-388 |
| 文件页数： | 9/47页 |
| 文件大小： | 747K |
| 代理商： | STPCC0175BTI3 |
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PIN DESCRIPTION
17/47
Issue 1.6
DEV_CLK
24MHz
Peripheral
Clock
Output. This 24MHZ signal is provided as
a convenience for the system integration
of a Floppy Disk driver function in an
external chip.
3.2.2.
MEMORY INTERFACE
MA[11:0]
Memory
Address
Output.
These 12 multiplexed memory address
pins support external DRAM with up to
4K refresh. These include all 16M x N
and some 4M x N DRAM modules. The
address
signals
must
be
externally
buffered to support more than 16 DRAM
chips. The timing of these signals can be
adjusted by software to match the timings
of most DRAM modules.
MD[63:0]
Memory Data I/O. This is the
64-bit memory data bus. If only half of a
bank is populated, MD63-32 is pulled
high, data is on MD31-0.
MD[40-0] are read by the device strap
option registers during rising edge of
PWGD.
RAS#[3:0]
Row Address Strobe Output.
There are 4 active low row address
strobe outputs, one for each bank of the
memory. Each bank contains 4 or 8-
Bytes of data. The memory controller
allows half of a bank (4-Bytes) to be
populated to enable memory upgrade at
finer granularity.
The RAS# signals drive the SIMMs
directly without any external buffering.
These pins are always outputs, but they
can also simultaneously be inputs, to
allow the memory controller to monitor
the value of the RAS# signals at the pins.
CAS#[7:0]
Column
Address
Strobe
Output. There are 8 active low column
address strobe outputs, one for each
Byte of the memory.
The CAS# signals drive the SIMMs either
directly or through external buffers.
These pins are always outputs, but they
can also simultaneously be inputs, to
allow the memory controller to monitor
the value of the CAS# signals at the pins.
MWE#
Write
Enable
Output.
Write
enable specifies whether the memory
access is a read (MWE# = H) or a write
(MWE# = L). This single write enable
controls all DRAMs. It can be externally
buffered to boost the maximum number
of loads (DRAM chips) supported.
The MWE# signals drive the SIMMs
directly without any external buffering.
3.2.3.
VIDEO INPUT
VCLK
Pixel Clock Input.
VIDEO_D[7:0]
YUV Video Data Input
CCIR 601 or 656. Time multiplexed 4:2:2
luminance and chrominance data as
defined in ITU-R Rec601-2 and Rec656
(except for TTL input levels). This bus
interfaces with an MPEG video decoder
output port and typically carries a stream
of Cb,Y,Cr,Y digital video at VCLK
frequency, clocked on the rising edge (by
default) of VCLK. A 54-Mbit/s ‘double’
Cb, Y, Cr, Y input multiplex is supported
for double encoding applications (rising
and
falling
edge
of
CKREF
are
operating).
3.2.4.
TV OUTPUT
TV_YUV[7:0]
Digital video outputs.
VTV_BT#
Frame Synchronization.
VTV_HSYNC
Horizontal
Line
Synchronization.
3.2.5.
PCI INTERFACE
PCI_CLKI
33MHz PCI Input Clock
This signal is the PCI bus clock input and
should be driven from the PCI_CLKO pin.
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