参数资料
型号: TDA8757AHL/21
厂商: NXP SEMICONDUCTORS
元件分类: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封装: PLASTIC, HLQFP-144
文件页数: 20/37页
文件大小: 908K
代理商: TDA8757AHL/21
Philips Semiconductors
TDA8757A
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 22 March 2002
27 of 37
9397 750 09549
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
[1]
From 25 to 70
°C, the edge of the clock CKDATA has a shift of 1 phase compared to CKREF.
[2]
Effective bits are obtained from a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST frequency).
Conversion-to-noise ratio: S/N = EB
× 6.02 + 1.76 dB.
[3]
Output data acquisition: the output data is available after the maximum sampling delay time td(s). All the timings are given for a 10 pF
capacitive load.
[4]
Pulse relative to the blank level.
[5]
The I2C-bus timings are given for use of the bus at a frequency of 100 kbit/s (100 kHz). This bus could be used at a frequency of
400 kbit/s (400 kHz).
Sync on green input
Vsync(G)
sync on green pulse amplitude [4]
Slevel = 0; see Figure 5
300
600
mV
Slevel = 1; see Figure 5
150
300
mV
3W-bus
trst
reset time of the chip before
3-wire communication
600
ns
tsu
data set-up time for 3-wire
communication
100
ns
th
data hold time for 3-wire
communication
100
ns
I2C-bus [5]
VIL
LOW-level input voltage
for SCL and SDA
0.3VDD
V
VIH
HIGH-level input voltage
for SCL and SDA;
VPU =5V
3
V
for SCL and SDA;
VPU =3V
0.7VDD
fSCL
clock frequency
0
100
kHz
tBUF
time the bus must be free before
new transmission can start
4.7
s
tHD;STA
start condition hold time
4.0
s
tSU;STA
start condition set-up time
repeated start
4.7
s
tLOW
LOW-level clock period
4.7
s
tHIGH
HIGH-level clock period
4.0
s
tSU;DAT
data set-up time
250
ns
tHD;DAT
data hold time
0
ns
tr
SDA and SCL rise time
fSCL = 100 kHz
1.0
s
tf
SDA and SCL fall time
fSCL = 100 kHz
300
ns
tSU;STO
stop condition set-up time
4.0
s
Cb
bus line capacitive loading
400
pF
Table 17: Characteristics…continued
VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V
(referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together;
Tamb = 0 to 70 °C; typical values measured at VCCA =VDDD =VCCD =VCCO = 5 V and Tamb =25 °C; unless otherwise
specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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