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| 型号： | TDA8757AHL/21 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封装： | PLASTIC, HLQFP-144 |
| 文件页数： | 6/37页 |
| 文件大小： | 908K |
| 代理商： | TDA8757AHL/21 |
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Philips Semiconductors
TDA8757A
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 22 March 2002
14 of 37
9397 750 09549
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
8.2.3
ADCs
Three ADCs convert analog signals into three series of 8-bit codes, with a maximum
clock frequency of 205 Msps. The ADCs input range is 1 V (p-p) full-scale and the
pipeline delay is 1 clock cycle from the sampling to the data output. The reference
ladders regulators are integrated.
8.2.4
Data outputs
ADC outputs are straight binary. Pin OE enables to switch the output status between
active and high-impedance (OE = HIGH). It is possible to force the outputs with a
maximum 10 pF capacitive load. The timing must be checked very carefully if the
capacitive loads are more than 10 pF.
It is possible to force the outputs to logic 0 during the gain calibration (during HSYNC
pulse) and during the clamping (CLP pulse). This mode is activated through the serial
interface by setting bit ‘Blk’ to logic 1 in register DEMUX.
The TDA8757A provides outputs either on one port (port A) or on two ports (ports A
and B). The selection is made with the serial interface by setting bit ‘Dmx’ to logic 0 or
logic 1 in register DEMUX. When just one port is used (Dmx = 0), the unused ports
are forced to LOW level. When two ports are used (Dmx = 1), it is possible to select
the port that would provide the odd pixel by setting bit ‘Odda’ to logic 1 or logic 0 in
register DEMUX; when this bit is logic 1, odd pixel on output of port A.
One out-of-range bit exists per channel (ORR, ORG and ORB). It will be at logic 1
when the signal is out-of-range of the ADC voltage ladder.
Finally, two congurations are possible: either the port A outputs and the port B
outputs are both synchronous or they are interleaved. The selection is done by
setting bit ‘Shift’ to logic 0 or logic 1 in register DEMUX.
8.2.5
PLL
The ADCs are clocked by either the internal PLL locked to the reference clock
CKREF or an external clock connected to pin CKEXT. All parts of the PLL are on-chip
except the loop lter capacitance. The selection is performed via the serial interface
by setting bit ‘Ckext’ in register PHASE (Ckext = 1 when the external clock is used).
Fig 7.
Denition of odd and even pixels; Edge = 0, Dmx = 0 and Ckrp = 1.
FCE708
CKADC
CKREF
CKREFO
OUT A
XXX
ODD
EVEN
XXX
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相关代理商/技术参数 |
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|---|---|
| TDA8757HL | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Triple 8-bit ADC 170 Msps |
| TDA8758 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:YC 8-bit low-power analog-to-digital video interface |
| TDA8758G | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:YC 8-bit low-power analog-to-digital video interface |
| TDA8759HV/8/C1 | 功能描述:模数转换器 - ADC 3X8-BITS VIDEO ADC 110MSPS RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TDA8759HV/8/C1,551 | 功能描述:模数转换器 - ADC 3X8-BITS VIDEO RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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