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| 型号： | TDA8757AHL/21 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封装： | PLASTIC, HLQFP-144 |
| 文件页数： | 7/37页 |
| 文件大小： | 908K |
| 代理商： | TDA8757AHL/21 |
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Philips Semiconductors
TDA8757A
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 22 March 2002
15 of 37
9397 750 09549
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
The reference clock (CKREF) range is between 15 and 150 kHz. Consequently, the
VCO minimum frequency is 12 MHz and the maximum frequency is 205 MHz. The
gain of the VCO part can be controlled through the serial interface, depending on the
frequency range to which the PLL is locked.
Moreover, the PLL may be locked either on the rising or on the falling edge of the
CKREF signal pulses. This choice is made via the serial interface by setting bit ‘Edge’
in register CONTROL (rising edge when bit ‘Edge’ = 0).
The charge pump current (Icp) enables to increase the PLL bandwidth. It is
programmable through the serial interface by setting bits ‘Ip2’, ‘Ip1’ and ‘Ip0’ in the
control register (see Table 8).
Different resistance values (R) for the lter can also be programmed through the
serial interface by setting the bits ‘Z2’, ‘Z1’ and ‘Z0’ in register VCO (see Table 9).
To have optimal PLL performance, R and Icp must be chosen so that:
The result of the product ‘R × Icp’ is smaller than a determined limit (Lim)
The result of the product ‘R × Icp’ is as close as possible to this limit (Lim).
(1)
where:
DRPLL = the divider ratio, which is the ratio between the pixel frequency and the
horizontal line frequency of the incoming signal. The setting of this parameter is
performed through the serial interface with bits Di0 to Di11. These bits are present
in the VCO-, divider- and phase registers.
fref = the frequency of the signal.
K0 = the VCO gain, which depends on the pixel frequency ranges given in
In the event that several combinations of R and Icp give the same result, a calculating
of the damping factor (
ξ) for each couple becomes necessary.
The combination of R and Icp whose damping factor is the closest to 1.5, generates
the optimal PLL performance.
(2)
where CZ and CP are the external capacitors of the PLL loop lter. The recommended
values are: CZ = 68 nF and CP = 150 pF.
Pin COAST is used to disconnect the PLL phase frequency detector during the frame
yback (vertical blanking) or the unavailability of the CKREF signal. This signal can
normally be derived from the VSYNC signal.
The COAST signal may be active either HIGH or LOW by setting bit ‘Vlevel’ in the
control register, through the serial interface (Vlevel = 0 when HIGH).
Lim
0.3
π DR
PLL
×
f
ref
×
K
0
--------------------------------------------------
=
ξ
RC
Z
2
---------------
K
0
I
cp
DR
PLL
C
Z
C
P
+
()
-----------------------------------------------
=
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| TDA8759HV/8/C1 | 功能描述:模数转换器 - ADC 3X8-BITS VIDEO ADC 110MSPS RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TDA8759HV/8/C1,551 | 功能描述:模数转换器 - ADC 3X8-BITS VIDEO RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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