参数资料
型号: TMP86CH47IUG
厂商: Toshiba Corporation
英文描述: Zener Diode; Application: General; Pd (mW): 500; Vz (V): 17.5 to 18.3; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
中文描述: 8位微控制器
文件页数: 107/160页
文件大小: 1627K
代理商: TMP86CH47IUG
Page 99
TMP86CH47IUG
9.3.9
Warm-Up Counter Mode
In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is
switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a
16-bit TimerCounter. The warm-up counter mode has two types of mode; switching from the high-frequency
to low-frequency, and vice-versa.
Note 1: In the warm-up counter mode, fix TCiCR<TFFi> to 0. If not fixed, the
PDOi
,
PWMi
and
PPGi
pins may output
pulses.
Note 2: In the warm-up counter mode, only upper 8 bits of the timer register TTREG4 and 3 are used for match
detection and lower 8 bits are not used.
Note 3: i = 3, 4
9.3.9.1
Low-Frequency Warm-up Counter Mode
(NORMAL1
NORMAL2
SLOW2
SLOW1)
In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability
is obtained. Before starting the timer, set SYSCR2<XTEN> to 1 to oscillate the low-frequency clock.
When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer
is started by setting TC4CR<TC4S> to 1, the counter is cleared by generating the INTTC4 interrupt
request. After stopping the timer in the INTTC4 interrupt service routine, set SYSCR2<SYSCK> to 1 to
switch the system clock from the high-frequency to low-frequency, and then clear of SYSCR2<XEN> to
0 to stop the high-frequency clock.
Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz)
Minimum Time Setting
(TTREG4, 3 = 0100H)
Maximum Time Setting
(TTREG4, 3 = FF00H)
7.81 ms
1.99 s
Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode
SET
(SYSCR2).6
: SYSCR2<XTEN>
1
LD
(TC3CR), 43H
: Sets TFF3=0, source clock fs, and 16-bit mode.
LD
(TC4CR), 05H
: Sets TFF4=0, and warm-up counter mode.
LD
(TTREG3), 8000H
: Sets the warm-up time.
(The warm-up time depends on the oscillator characteristic.)
DI
: IMF
0
SET
(EIRH). 1
: Enables the INTTC4.
EI
: IMF
1
SET
(TC4CR).3
: Starts TC4 and 3.
:
:
PINTTC4:
CLR
(TC4CR).3
: Stops TC4 and 3.
SET
(SYSCR2).5
: SYSCR2<SYSCK>
1
(Switches the system clock to the low-frequency clock.)
CLR
(SYSCR2).7
: SYSCR2<XEN>
0 (Stops the high-frequency clock.)
RETI
:
:
VINTTC4:
DW
PINTTC4
: INTTC4 vector table
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