参数资料
型号: TMP86CH47IUG
厂商: Toshiba Corporation
英文描述: Zener Diode; Application: General; Pd (mW): 500; Vz (V): 17.5 to 18.3; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
中文描述: 8位微控制器
文件页数: 86/160页
文件大小: 1627K
代理商: TMP86CH47IUG
Page 78
8. 16-Bit TimerCounter 1 (TC1)
8.3 Function
TMP86CH47IUG
Figure 8-7
PPG
Output
Example :Generating a pulse which is high-going for 800 μs and low-going for 200
μ
s
(fc = 16 MHz)
Setting port
LD
(TC1CR), 10000111B
; Sets the PPG mode, selects the source clock
LDW
(TC1DRA), 007DH
; Sets the cycle (1 ms
÷
2
7
/fc ms = 007DH)
LDW
(TC1DRB), 0019H
; Sets the low-level pulse width (200
μ
s
÷
2
7
/fc = 0019H)
LD
(TC1CR), 10010111B
; Starts the timer
Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG
(fc = 16 MHz)
Setting port
LD
(TC1CR), 10000111B
; Sets the PPG mode, selects the source clock
LDW
(TC1DRA), 007DH
; Sets the cycle (1 ms
÷
2
7
/fc
μ
s = 007DH)
LDW
(TC1DRB), 0019H
; Sets the low-level pulse width (200
μ
s
÷
2
7
/fc = 0019H)
LD
(TC1CR), 10010111B
; Starts the timer
:
:
LD
(TC1CR), 10000111B
; Stops the timer
LD
(TC1CR), 10000100B
; Sets the timer mode
LD
(TC1CR), 00000111B
; Sets the PPG mode, TFF1 = 0
LD
(TC1CR), 00010111B
; Starts the timer
Q
R
D
PPG pin
Function output
Port output
enable
I/O port output latch
shared with PPG output
Data output
Toggle
Set
Clear
Q
TC1CR<TFF1>
Write to TC1CR
Internal reset
Match to TC1DRB
Match to TC1DRA
TC1CR<TC1S> clear
Timer F/F1
INTTC1 interrupt request
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