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参数资料
| 型号： | TMS470R1VF346BPZQ |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | PLASTIC, LQFP-100 |
| 文件页数： | 22/56页 |
| 文件大小： | 779K |
| 代理商： | TMS470R1VF346BPZQ |
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TMS470R1VF336A, TMS470R1VF346A
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS079I – OCTOBER 2002 – REVISED SEPTEMBER 2006
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
ZPLL and clock specifications
timing requirements for ZPLL circuits enabled or disabled
Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal
to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number
SPNU189).
switching characteristics over recommended operating conditions for clocks§
f(SYS) = M × f(OSC) / R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the CLKDIVPRE
[2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the GLBCTRL register
(GLBCTRL.3).
f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits
in the SYS module.
§f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
# Flash Vread must be set to 5V to achieve maximum System Clock Frequency.
MIN
MAX
UNIT
f(OSC)
Input clock frequency
420
MHz
tc(OSC)
Cycle time, OSCIN
50
ns
tw(OSCIL)
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
ns
f(OSCRST)
OSC FAIL frequency
53
kHz
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
f(SYS)
System clock frequency#
Pipeline mode enabled
48
MHz
Pipeline mode disabled
28
f(CONFIG)
System clock frequency - flash config mode
24
MHz
f(ICLK)
Interface clock frequency
Pipeline mode enabled
25
MHz
Pipeline mode disabled
24
f(ECLK)
External clock output frequency for ECP Module
Pipeline mode enabled
25
MHz
Pipeline mode disabled
24
tc(SYS)
Cycle time, system clock
Pipeline mode enabled
20.8
ns
Pipeline mode disabled
35.7
tc(CONFIG)
Cycle time, system clock - flash config mode
41.6
ns
tc(ICLK)
Cycle time, interface clock
Pipeline mode enabled
40
ns
Pipeline mode disabled
41.6
tc(ECLK)
Cycle time, ECP module external clock output
Pipeline mode enabled
40
ns
Pipeline mode disabled
41.6
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相关代理商/技术参数 |
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