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参数资料
| 型号： | TMS470R1VF346BPZQ |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | PLASTIC, LQFP-100 |
| 文件页数： | 3/56页 |
| 文件大小： | 779K |
| 代理商： | TMS470R1VF346BPZQ |
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TMS470R1VF336A, TMS470R1VF346A
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS079I – OCTOBER 2002 – REVISED SEPTEMBER 2006
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
Terminal Functions (Continued)
I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
TERMINAL
TYPE
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
NAME
VF336A
VF346A
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
AWD
50
3.3-V I/O
IPD
Analog watchdog reset. The AWD pin provides a system reset if the WD
KEY is not written in time by the system, providing an external RC network
circuit is connected. If the user is not using AWD, TI recommends that this
pin be connected to ground or pulled down to ground by an external
resistor.
For more details on the external RC network circuit, see the TMS470R1x
System Module Reference Guide (literature number SPNU189) and the
application note Analog Watchdog Resistor, Capacitor and Discharge
Interval Selection Constraints (literature number SPNA005).
TEST/DEBUG (T/D)
TCK
54
3.3-V I
IPD
Test clock. TCK controls the test hardware (JTAG)
TDI
52
3.3-V I
IPU
Test data in. TDI inputs serial data to the test instruction register, test data
register, and programmable test address (JTAG).
TDO
53
3.3-V O
IPD
Test data out. TDO outputs serial data from the test instruction register,
test data register, identification register, and programmable test address
(JTAG).
TEST
27
3.3-V I
IPD
Test enable. Reserved for internal use only. TI recommends that this pin
be connected to ground or pulled down to ground by an external resistor.
TMS
84
87
3.3-V I
IPU
Serial input for controlling the state of the CPU test access port (TAP)
controller (JTAG)
TMS2
85
88
3.3-V I
IPU
Serial input for controlling the second TAP. TI recommends that this pin
be connected to VCCIO or pulled up to VCCIO by an external resistor.
TRST
26
3.3-V I
IPD
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)
Boundary-Scan Logic. TI recommends that this pin be pulled down to
ground by an external resistor.
FLASH
FLTP1
93
95
NC
Flash test pads 1 and 2. For proper operation, these pins must not be
connected [no connect (NC)].
FLTP2
92
94
VCCP
94
96
3.3-V
PWR
Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
VCC
99
1.8-V
PWR
Core logic supply voltage
40
66
65
87
90
91
93
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
VCCIO
12
3.3-V
PWR
Digital I/O supply voltage
58
57
SUPPLY GROUND CORE
VSS
66
GND
Core supply ground reference
39
65
64
86
89
90
92
SUPPLY GROUND DIGITAL I/O
VSSIO
11
GND
Digital I/O supply ground reference
57
56
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相关代理商/技术参数 |
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| TMS470R1VF348 | 制造商:TI 制造商全称:Texas Instruments 功能描述:16/32-BIT RISC FLASH MICROCONTROLLERS |
| TMS470R1VF3482 | 制造商:TI 制造商全称:Texas Instruments 功能描述:16/32-BIT RISC FLASH MICROCONTROLLERS |
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