参数资料
型号: TMS470R1VF346BPZQ
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 48 MHz, RISC MICROCONTROLLER, PQFP100
封装: PLASTIC, LQFP-100
文件页数: 24/56页
文件大小: 779K
代理商: TMS470R1VF346BPZQ
TMS470R1VF336A, TMS470R1VF346A
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS079I – OCTOBER 2002 – REVISED SEPTEMBER 2006
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
ZPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for external clocks
X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.
N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
§ CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).
# Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary).
Figure 5. CLKOUT Timing Diagram
Figure 6. ECLK Timing Diagram
NO.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
1
tw(COL)
Pulse duration, CLKOUT low
SYSCLK or MCLK
0.5tc(SYS) – tf
ns
ICLK, X is even or 1#
0.5tc(ICLK) – tf
ICLK, X is odd and not 1#
0.5tc(ICLK)+ 0.5tc(SYS) – tf
2
tw(COH)
Pulse duration, CLKOUT high
SYSCLK or MCLK
0.5tc(SYS) – tr
ns
ICLK, X is even or 1#
0.5tc(ICLK) – tr
ICLK, X is odd and not 1#
0.5tc(ICLK)– 0.5tc(SYS) – tr
3
tw(EOL)
Pulse duration, ECLK low
N is even and X is even or odd
0.5tc(ECLK) – tf
ns
N is odd and X is even
0.5tc(ECLK) – tf
N is odd and X is odd and not 1
0.5tc(ECLK)+ 0.5tc(SYS) – tf
4
tw(EOH)
Pulse duration, ECLK high
N is even and X is even or odd
0.5tc(ECLK) – tr
ns
N is odd and X is even
0.5tc(ECLK) – tr
N is odd and X is odd and not 1
0.5tc(ECLK)– 0.5tc(SYS) – tr
CLKOUT
1
2
ECLK
3
4
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