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| 型号： | TPS65040ZQER |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71 |
| 封装： | 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71 |
| 文件页数： | 16/73页 |
| 文件大小： | 1928K |
| 代理商： | TPS65040ZQER |
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ELECTRICAL CHARACTERISTICS (continued)
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
Over recommended input conditions, T
A = –30°C to 85°C, typical values are VBAT = 3.8 V, VIO1V8 = 1.85 V at TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREF1, VREF2(1)
Output voltage of VREF1
VO(REF1)
Sub bandgap on, Main bandgap on(2)
1.235
1.242
1.248
V
pin
Sub bandgap on, Main bandgap on(2)
1.235
1.242
1.248
V
Output voltage of VREF2
VO(REF2)
pin
Sub bandgap on , Main bandgap off(3)
1.233
1.246
1.258
V
ISD
Shutdown current(4)
VBN1 pin at TA = 25°C
1
A
Sub bandgap on, Main bandgap on(2), VBN1 pin at
IQ
Quiescent current
53
87
A
TA = 25°C
Sub bandgap on, Main bandgap off(3), VBN1 pin at
17
42
A
TA = 25°C
REG_EN pin = 0V to VBAT(5),
150
250
s
COVREF1 = 0.01 F
tST(REF1)
Power up from low power mode to normal mode or
Startup time
r[PSCNTDC/DC] = 0 to 1(6),
60
160
s
COVREF1 = 0.01 F
tST(REF2)
REG_EN pin = 0V to VBAT(5), COVREF2 = 0.1 F
200
350
s
VBAT UNDERVOLTAGE ELECTRICAL CHARACTERISTICS (2.7 V < VBAT < 3.1 V)
Output voltage of VREF1
VO(REF1)
Sub bandgap on , Main bandgap on(2)
1.242
V
pin
Sub bandgap on , Main bandgap on(2)
1.242
V
Output voltage of VREF2
VO(REF2)
pin
Sub bandgap on , Main bandgap off(3)
1.246
V
REG_EN pin = 0V to VBAT(5),
300
s
COVREF1 = 0.01 F
tST(REF1)
Power up from Low Power Mode to Normal Mode or
Startup time
r[PSCNTDC/DC] = 0 to 1(6),
200
s
COVREF1 = 0.01 F
tST(REF2)
REG_EN pin = 0V to VBAT(5), COVREF2 = 0.1 F
450
s
THERMAL SHUTDOWN(7)
THD
Shutdown temperature
Increasing junction temperature
145
160
175
°C
THDrel
Releasing temperature
Decreasing junction temperature
135
150
165
°C
THDHYS
Temperature hysteresis
10
°C
HOT DIE DETECTION(7)
HDD1
Hot-die detection1
95
110
125
°C
HDD2
Hot-die detection2
105
120
135
°C
HDD3
Hot-die detection3
115
130
145
°C
HDD4
Hot-die detection4
125
140
155
°C
HDD5
Hot-die detection5
135
150
165
°C
HDDHYS
Temperature hysteresis
10
°C
(1)
VREF1 pin and VREF2 pin must not connect to other devices.
(2)
Some block is powered up by a register command which is written from serial interface, or SYSCLK_EN pin, or TXONFST pin is VVIO.
If r[PSCNTDC/DC]=0, VREF1 pin is 0 V. More detail is provided in the VREF1, VREF2 Section.
(3)
All blocks are powered down by register commands which are written from serial interface and SYSCLK_EN, TXONFST and TXON pins
are 0V. Or V12_V28RX, V13_V28A, V15_V18A, VGGE1_V28, VGGE2_V28 and VGGE3_V28 are Low Power Mode, and other blocks
are powered down by register command which is written from serial interface and SYSCLK_EN, TXONFST and TXON pins are 0V.
More detail is given in the VREF1, VREF2 Section.
(4)
REG_EN pin = Low, include PAVREF and AFCDAC
(5)
Power up sequence by starting from REG_EN pin = 0 V to VBAT. More detail is given in the VREF1, VREF2 Section.
(6)
When the Low Power Mode or r[PSCNTDC/DC] = 0, VREF1 pin is powered down. More detail is given in VREF1, VREF2 Section. The
start up of the r[PSCNTDC/DC] control is not production tested.
(7)
Not production tested. Specified by using the reference EVM.
23
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