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参数资料
| 型号： | TPS65073TRSLRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封装： | 6 X 6 MM, 0.4 MM PITCH, PLASTIC, QFN-48 |
| 文件页数： | 51/90页 |
| 文件大小： | 1375K |
| 代理商： | TPS65073TRSLRQ1 |
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SLVSAP7 – JANUARY 2011
CON_CTRL2. Register Address: 0Eh
CON_CTRL2
B7
B6
B5
B4
B3
B2
B1
BO
ENABLE
UVLO
PWR_D
Bit name and function
DS_RDY
MASK_EN_DCDC3
UVLO1
UVLO0
S
1s timer
5s timer
hysteresis
Default value loaded
UVLO
BG_GOOD
by:
Read/write
R/W
Bit 7…6
ENABLE TIMERS:
0 = the state machine timers of 1s and 5s, respectively are disabled
1 = the state machine timers of 1s and 5s, respectively are enabled
Bit 5
DS_RDY (data ready, memory content valid) for use with Sirf Prima processor DEEP SLEEP
mode:
0 = status Bit which is indicating the memory content is not valid after wake up from DEEP SLEEP.
This Bit is set / cleared by the Prima application processor. Cleared when device is in UVLO to tell
processor there was a power loss. The Bits needs to be cleared by user software after a wake up
from DEEP SLEEP to enable the DCDC2 converter to be powered down in shutdown sequencing
depending on the status of LDO2.
1 = memory content is valid after wake up from DEEP SLEEP (set by I2C command by application
processor only). The Prima processor is ready to power down to DEEP SLEEP mode or was just
waking up from DEEP SLEEP mode.
Bit 4
PWR_DS (enter DEEP SLEEP for sequencing option DCDC_SEQ=100, LDO_SQ=111):
0 = PMU is in normal operation
1 = PMU powers down all rails except DCDC2 and the external LDO on pin “EXT_LDO”. PGOOD
is pulled LOW.
Bit 3
MASK_EN_DCDC3; used for Prima application processor start-up sequencing:
0 = DCDC3 is enabled or disabled by the status of EN_DCDC3 for sequencing option
DCDC_SEQ=100.
1 = DCDC3 will start at the same time with LDO2 for sequencing option DCDC_SEQ=100. The
status of EN_DCDC3 is ignored
Bit 2
UNDERVOLTAGE LOCKOUT HYSTERESIS:
0 = 400mV hysteresis
1 = 500mV hysteresis
Bit 1..0
UVLO1, UVLO2 (undervoltage lockout voltage):
00 = the device turns off at 2.8V with the reverse of the sequencing defined in CON_CTRL1
01 = the device turns off at 3.0V with the reverse of the sequencing defined in CON_CTRL1
10 = the device turns off at 3.1V with the reverse of the sequencing defined in CON_CTRL1
11 = the device turns off at 3.25V with the reverse of the sequencing defined in CON_CTRL1
Note: The undervoltage lockout voltage is sensed at the SYS pin and the device goes to OFF state when
the voltage is below the value defined in the register. BG_GOOD is the internal bandgap good
signal which occurs at lower voltages than UVLO.
Copyright 2011, Texas Instruments Incorporated
55
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