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参数资料
| 型号： | TPS65073TRSLRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封装： | 6 X 6 MM, 0.4 MM PITCH, PLASTIC, QFN-48 |
| 文件页数： | 57/90页 |
| 文件大小： | 1375K |
| 代理商： | TPS65073TRSLRQ1 |
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SLVSAP7 – JANUARY 2011
www.ti.com
LDO_CTRL1. Register Address: 16h
LDO_CTRL1
B7
B6
B5
B4
B3
B2
B1
BO
Bit name and function
LDO_SQ2
LDO_SQ1
LDO_SQ0
LDO1[3]
LDO1[2]
LDO1[1]
LDO1[0]
Default value loaded by:
UVLO
Read/write
R/W
R
R/W
Bit 7..5
LDO_SQ2 to LDO_SQ0: power-up sequencing: (power down sequencing is the reverse)
000 = LDO1 and LDO2 are enabled as soon as device is in ON-state by pulling PB_IN=LOW or
POWER_ON=HIGH
001 = LDO1 and LDO2 are enabled after DCDC3 was enabled and its power good Bit is high.
010 = external pin at “EN_EXTLDO” is driven HIGH first, after >1ms LDO2 is enabled, LDO1 is
enabled at the same time with DCDC3. EN_EXTLDO is driven LOW by going into OFF-state, LDO2
is disabled at the same time with EN_EXTLDO going LOW. Disabling LDO2 in register CON_CTRL1
will not drive EN_EXTLDO=LOW. (Atlas4)
011 = LDO1 is enabled 300us after PGOOD of DCDC1, LDO2 is off. LDO2 can be enabled/disabled
by an I2C command in register CON_CTRL1.
100 = LDO1 is enabled after DCDC1 shows power good; LDO2 is enabled with DCDC3
101 = LDO1 is enabled with DCDC2; LDO2 is enabled after DCDC1 is enabled and its power good
Bit is high
110 = LDO1 is enabled 10ms after DCDC2 is enabled and its power good Bit is high, LDO2 is off.
LDO2 can be enabled / disabled by an I2C command in register CON_CTRL1.
111 = external pin at EN_EXTLDO is driven HIGH first, after >1ms LDO2 is enabled, LDO1 is
enabled when EN_DCDC3 pin is pulled high AND DCDC3 is power good (first power–up from OFF
state). LDO1 is disabled when EN_DCDC3 pin goes LOW for SLEEP mode. LDO2 is disabled at the
same time with DCDC2 and DCDC1 during shutdown (Sirf PRIMA).
Automatic sequencing sets the enable Bits of the LDOs accordingly, so the LDOs can be enabled or disabled
by the I2C interface in ON-state.
All sequencing options that define a ramp in sequence for the DCDC converters and the LDOs, (not at the
same time) are timed such that the power good signal triggers the start for the next converter. If there is a time
defined such as 1ms delay, the timer is started after the power good signal of the previous converter is high.
LDO enable is delayed by 170us internally to match the delay for the DCDC converters. By this, for sequencing
options that define a ramp at the same time for an LDO and a DCDC converter, it is made sure they will ramp
at the same time, given the fact the DCDC converters have an internal 170us delay as well.
60
Copyright 2011, Texas Instruments Incorporated
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