- 您现在的位置：买卖IC网 > PDF目录272833 > TPS65073TRSLRQ1 (TEXAS INSTRUMENTS INC) POWER SUPPLY SUPPORT CKT, PQCC48 PDF资料下载
参数资料
| 型号： | TPS65073TRSLRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封装： | 6 X 6 MM, 0.4 MM PITCH, PLASTIC, QFN-48 |
| 文件页数： | 73/90页 |
| 文件大小： | 1375K |
| 代理商： | TPS65073TRSLRQ1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页当前第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页
www.ti.com
SLVSAP7 – JANUARY 2011
Prima SLEEP Mode and DEEP SLEEP Mode Support
TPS6507x contains a sequencing option for the Sirf Prima processor. The sequencing option defines how the
voltages are ramped at initial power-up and shutdown as well as the timing for entering power save mode for the
processor (SLEEP mode). The Prima processor supports SLEEP mode and also DEEP SLEEP mode. The main
difference from a power supply point of view is:
How the supply voltages are turned off
Which voltages are turned off
How power save mode is exited into normal mode
Reset asserted or not (PGOOD pin of TPS6507x going actively low)
The sequencing option for Prima is defined in one register each for the sequencing of the DCDC converters and
for the LDOs. DCDC_SQ[2..0]=100 in register CON_CTRL1 defines the startup sequence for the DCDC
converters while LDO_SQ[2..0]=111 defines the sequence for the LDOs. The default is factory programmed
therefore it is ensured the first power-up is done in the right sequence.
When TPS6507x is off, a small state machine supervises the status of pin PB_IN while major blocks are not
powered for minimum current consumption from the battery as long as there is no input voltage to the charger.
Power-up for the TPS6507x is started by PB_IN going LOW. This will turn on the power-FET from the battery so
the system voltage (SYS) is rising and the main blocks of the PMU are powered. After a debounce time of 50ms,
the main state machine will pull PB_OUT = LOW to indicate that there is a “keypress” by the user and will ramp
the DCDC converters and LDOs according to the sequence programmed. It is important to connect the power
rails for the processor to exactly the dcdc converters and LDOs as shown in the schematic and sequencing
diagrams for proper sequencing. For Prima, the voltage rails for VDD_RTCIO needs to ramp first. This power rail
is not provided by the PMU but from an external LDO which is enabled by a signal called EN_EXTLDO from the
PMU. The PMU will therefore first rise the logic level an pin EN_EXTLDO high to enable the external LDO. After
a 1ms delay the PMU will ramp LDO2 for VDD_PRE and DCDC3 for VDD_PDN. When the output voltage of
LDO2 is within it s nominal range the internal power good comparator will trigger the state machine which will
ramp DCDC1 and DCDC2 to provide the supply voltage for VCC_3V3 and VCC_1V8. Now Prima needs to pull
its X_PWR_EN signal high which drives EN_DCDC3 on the PMU. This will now enable LDO1 to power VDDPLL.
X_RESET_B will be released by the PMU on pin PGOOD based on the voltage of DCDC1 after a delay of 20ms.
SLEEP Mode
At first power-up (start-up from OFF state), the voltage for VDD_PDN is ramped at the same time than
VDD_PRE. This is defined by Bit MASK_EN_DCDC3 in register CON_CTRL2 which is “1” per default. For
enabling SLEEP mode, Prima needs to clear this Bit, so the EN_DCDC3 pin takes control over the DCDC3
converter. Prima SLEEP mode is initialized by Prima pulling its X_PWR_EN pin LOW which is driving the
EN_DCDC3 pin of TPS6507x. This will turn off the power for VDDPLL (LDO1) and also for VDD_PDN (DCDC3).
All other voltage rails will stay on. Based on a “keypress” with PB_OUT going LOW, Prima will wake up and
assert EN_DCDC3=HIGH. This will turn DCDC3 and LDO1 back on and Sirf PRIMA will enter normal operating
mode.
DEEP SLEEP Mode
Entry into DEEP SLEEP mode is controlled by Prima by writing to register CON_CTRL2 of TPS6507x. Before
entering DEEP SLEEP mode, Prima will back up all memory and set Bit DS_RDY=1 to indicate the memory was
saved and the content is valid. Setting PWR_DS=1 will turn off all voltage rails except DCDC2 for the memory
voltage and the PMU will apply a reset signal by pulling PGOOD=LOW. Prima can not detect logic level change
by PB_OUT going low in DEEP SLEEP mode. A wakeup from DEEP sleep is therefore managed by the PMU.
The PMU will clear Bit PWR_DS and turn on the converters again based on a user “keypress” when PB_IN is
being pulled LOW. Prima will now check if DS_RDY=1 to determine if the memory content is still valid and clear
the Bit afterwards. In case there is a power loss and the voltage of the PMU is dropping below the undervoltage
lockout threshold, the registers in the PMU are re-set to the default and DS_RDY is cleared. The PMU would
perform a start-up from OFF state instead of exit from DEEP SLEEP and Sirf PRIMA would read DS_RDY=0,
which indicates memory data is not valid.
See timing diagrams for Sirf Prima SLEEP and DEEP SLEEP in Figure 53 and Figure 54.
Copyright 2011, Texas Instruments Incorporated
75
相关PDF资料 |
PDF描述 |
|---|---|
| TC151A4924EOA713 | 0.25 A SWITCHING REGULATOR, 50 kHz SWITCHING FREQ-MAX, PDSO8 |
| TC161B3514EOA723 | 0.25 A SWITCHING REGULATOR, 100 kHz SWITCHING FREQ-MAX, PDSO8 |
| TC161B1717EOA713 | 0.25 A SWITCHING REGULATOR, 100 kHz SWITCHING FREQ-MAX, PDSO8 |
| TC161A5520EOA713 | 0.25 A SWITCHING REGULATOR, 100 kHz SWITCHING FREQ-MAX, PDSO8 |
| TC161A5825EOA713 | 0.25 A SWITCHING REGULATOR, 100 kHz SWITCHING FREQ-MAX, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TPS650830EVM-095 | 功能描述:TPS650830 - Power Management, Special Purpose: Mobiles Evaluation Board 制造商:texas instruments 系列:- 零件状态:有效 主要用途:电源管理，专用型： 手机 嵌入式:- 使用的 IC/零件:TPS650830 主要属性:- 辅助属性:图形用户接口，I2C 接口 所含物品:板 标准包装:1 |
| TPS650830ZAJT | 功能描述:- Converter, Mobile PCs Voltage Regulator IC 8 Output 168-NFBGA (7x7) 制造商:texas instruments 系列:- 包装:剪切带（CT） 零件状态:有效 应用:转换器，移动式个人电脑 电压 - 输入:5.4 V ~ 24 V 输出数:8 电压 - 输出:多重 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:168-TFBGA 供应商器件封装:168-NFBGA（7x7） 标准包装:1 |
| TPS650830ZCGT | 功能描述:- Converter, Mobile PCs Voltage Regulator IC 8 Output 159-NFBGA (9x9) 制造商:texas instruments 系列:- 包装:剪切带（CT） 零件状态:有效 应用:转换器，移动式个人电脑 电压 - 输入:5.4 V ~ 24 V 输出数:8 电压 - 输出:多重 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:159-TFBGA 供应商器件封装:159-NFBGA(9x9) 标准包装:1 |
| TPS650860A0RSKT | 功能描述:D-CAP2? Controller, Multicore, CPU, FPGA, SOC’s Voltage Regulator IC 8 Output 64-QFN (8x8) 制造商:texas instruments 系列:D-CAP2?? 包装:剪切带（CT） 零件状态:有效 应用:控制器，多核，CPU，FPGA，SOC 应用 电压 - 输入:4.5 V ~ 21 V 输出数:8 电压 - 输出:多重 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-VFQFN 裸露焊盘 供应商器件封装:64-QFN（8x8） 标准包装:1 |
| TPS650860EVM-116 | 功能描述:EVALUATION MODULE 制造商:texas instruments 系列:* 零件状态:在售 标准包装:1 |
发布紧急采购，3分钟左右您将得到回复。