参数资料
型号: TPS659107A1RSL
厂商: TEXAS INSTRUMENTS INC
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48
封装: 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, PLASTIC, VQFN-48
文件页数: 28/93页
文件大小: 1014K
代理商: TPS659107A1RSL
SWCS046-024
SLEEP
t
ACT2SLP
VIO/VFBIO
1.8 V
PWM mode
VAUX1
VDD2/VFB2
VDD1/VFB1
VPLL
VDAC
VAUX2
VMMC
CLK32KOUT
SWIO
SW2
SW1
1.8 V
Low-power mode
1.8 V
PWM mode
1.8 V
Active mode
1.8 V
Low-power mode
1.8 V
Active mode
3.3 V
Pulse skip mode
3.3 V
Low-power mode
3.3 V
1.2 V
PWM mode
Off
1.8 V
Active mode
1.8 V
Active mode
1.8 V
Active mode
3.3 V
Active mode
3.3 V
Low-power mode
Off
1.8 V
Active mode
1.8 V
Active mode
3.3 V
Active mode
1.2 V
PWM mode
1.8 V
Active mode
1.8 V
Active mode
t
SLP2ACT
t
SLP2ACTCK32K
t
dSLPON1
t
dSLPONST
t
dSLPONST
t
dONDCDCSLP
t
ACT2SLPCK32K
Pulse skip mode
SWCS046I
– MARCH 2010 – REVISED JULY 2011
Device SLEEP State Control
Figure 7 shows the device SLEEP state control timing characteristics.
NOTE: Registers programming: VIO_PSKIP = 0, VDD1_PSKIP = 0, VDD1_SETOFF = 1, VDAC_SETOFF = 1,
VPLL_SETOFF = 1, VAUX2_KEEPON = 1
Figure 7. Device SLEEP State Control
Table 7. Device SLEEP State Control Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SLEEP falling edge to supply in low power
2
× tCK32k =
3
× tCK32k =
tACT2SLP
mode
s
62
94
(SLEEP resynchronization delay)
tACT2SLP + 3 ×
tACT2SLP
SLEEP falling edge to CLK32KOUT low
156
188
s
tCK32k
SLEEP rising edge to supply in high power
8
× tCK32k =
9
× tCK32k =
tSLP2ACT
s
mode
250
281
tSLP2ACT + 3 ×
tSLP2ACTCK32K
SLEEP rising edge to CLK32KOUT running
344
375
s
tCK32k
SLEEP rising edge to time step 1 of the tun-on
tSLP2ACT + 1 ×
tdSLPON1
281
312
s
sequence from SLEEP state
tCK32k
turn-on sequence step duration, from SLEEP
state
TSLOT_LENGTH[1:0] = 00
0
tdSLPONST
s
TSLOT_LENGTH[1:0] = 01
200
TSLOT_LENGTH[1:0] = 10
500
TSLOT_LENGTH[1:0] = 11
2000
VDD1, VDD2 or VIO tun-on delay from tun-on
2
× tCK32k =
tdSLPONDCDC
us
sequence time step
62
34
Copyright
2010–2011, Texas Instruments Incorporated
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