参数资料
型号: TPS659107A1RSL
厂商: TEXAS INSTRUMENTS INC
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48
封装: 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, PLASTIC, VQFN-48
文件页数: 81/93页
文件大小: 1014K
代理商: TPS659107A1RSL
SWCS046I
– MARCH 2010 – REVISED JULY 2011
Bits
Field Name
Description
Type
Reset
7
RTC_PERIOD_IT_MS RTC period event interrupt mask.
RW
0
K
6
RTC_ALARM_IT_MS
RTC alarm event interrupt mask.
RW
0
K
5
HOTDIE_IT_MSK
Hot die event interrupt mask.
RW
0
4
PWRHOLD_IT_MSK
PWRHOLD rising edge event interrupt mask.
RW
0
3
PWRON_LP_IT_MSK
PWRON Long Press event interrupt mask.
RW
0
2
PWRON_IT_MSK
PWRON event interrupt mask.
RW
0
1
VMBHI_IT_MSK
VBAT
> VMBHI event interrupt mask.
RW
1
When 0, enable the device automatic switch on at BACKUP to OFF or
NOSUPPLY to OFF device state transition (EEPROM bit)
0
VMBDCH_IT_MSK
VBAT
< VMBDCH event interrupt status.
RW
0
Active only if the main battery comparator VMBCH programmable
threshold is not bypassed (VMBCH_SEL[1:0]
≠ 00).
Table 76. INT_STS2_REG
Address Offset
0x52
Physical Address
Instance
Description
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type
RW
7
6
5
4
3
2
1
0
Reserved
GPIO0_F_IT
GPIO0_R_IT
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
0
W1 to Clr
1
GPIO0_F_IT
GPIO_CKSYNC falling edge detection interrupt status
RW
0
W1 to Clr
0
GPIO0_R_IT
GPIO_CKSYNC rising edge detection interrupt status
RW
0
W1 to Clr
Table 77. INT_MSK2_REG
Address Offset
0x53
Physical Address
Instance
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
5
4
3
2
1
0
Reserved
GPIO0_F_IT_MSK
GPIO0_R_IT_MSK
82
Copyright
2010–2011, Texas Instruments Incorporated
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