参数资料
型号: TPS659107A1RSL
厂商: TEXAS INSTRUMENTS INC
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48
封装: 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, PLASTIC, VQFN-48
文件页数: 30/93页
文件大小: 1014K
代理商: TPS659107A1RSL
1.2 V
SCLSR_EN2
PFM (pulse
skipping) mode
SW1
VDD1/VFB1
0.8 V
PFM (pulse
skipping) mode
PFM (pulse skipping) mode
PWM mode
t
dDVSEN
t
dDVSENL
t
dDVSEN
TSTEP[2:0]=001
TSTEP[2:0]=011
t
dDVSENL
SWCS046-021
SWCS046-025
SW3
SW2
SWIO
SW1
t
dswio2sw1
t
dswio2sw2
t
dswio2sw3
t
dviosync
SWCS046I
– MARCH 2010 – REVISED JULY 2011
VDD1 and VDD2 Voltage Control Through SCLSR_EN1 and SDASR_EN2 Signals
Figure 10 shows the VDD1 and VDD2 voltage control through the SCLSR_EN1 and SDASR_EN2 signals timing
characteristics.
NOTE: Register setting: VDD1_EN1 = 1, SEL[6:0] = hex13 in VDD1_SR_REG
Figure 10. VDD1 Supply Voltage Control Though SCLSR_EN1
Table 9. VDD1 Supply Voltage Control Through SCLSR_EN1 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdDVSEN: SCLSR_EN1 or SCLSR_EN2 edge to
2
× tCK32k = 62
s
VDD1 or VDD2 voltage change delay
tdDVSENL: VDD1 or VDD2 voltage settling delay
TSTEP[2:0] = 001
32
s
TSTEP[2:0] = 011 (default)
0.4/7.5 = 53
TSTEP[2:0] = 111
160
SMPS Switching Synchronization
Figure 11 shows the SMPS switching synchronization timing characteristics.
NOTE: VDD1 or VDD2 switching synchronization is available in PWM mode (VDD1_PSKIP = 0 or VDD2_PSKIP = 0). SMPS
external clock (GPIO_CKSYNC) synchronization is available when VIO PWM mode is set (VIO_PSKIP = 0).
Figure 11. SMPS Switching Synchronization
Table 10. SMPS Switching Synchronization Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD1_PSKIP = 0,
tdSWIO2SW1: delay from SWIO rising edge to SW1
DCDCCKSYNC[1:0] = 11
160
ns
rising edge
DCDCCKSYNC[1:0] = 01
220
VDD2_PSKIP = 0,
tdSWIO2SW2: delay from SWIO rising edge to SW1
DCDCCKSYNC[1:0] = 11
160
ns
rising edge
DCDCCKSYNC[1:0] = 01
290
tdSWIO2SW3: delay from SWIO rising edge to SW3
206
ns
rising edge
36
Copyright
2010–2011, Texas Instruments Incorporated
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