- 您现在的位置：买卖IC网 > PDF目录69523 > TPS659107A1RSL (TEXAS INSTRUMENTS INC) 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48 PDF资料下载
参数资料
| 型号： | TPS659107A1RSL |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封装： | 6 X 6 MM, 1 MM HEIGHT, 0.40 MM PITCH, PLASTIC, VQFN-48 |
| 文件页数： | 38/93页 |
| 文件大小： | 1014K |
| 代理商： | TPS659107A1RSL |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页
SWCS046I
– MARCH 2010 – REVISED JULY 2011
Resources can be kept in their active mode: (full-load capability), programming the SLEEP_KEEP_LDO_ON and
the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per power resource. If the bit is set to 1,
then that resource stays in active mode when the device is in SLEEP state. 32KCLKOUT is also included in the
SLEEP_KEEP_RES_ON register and the 32-kHz clock output is maintained in SLEEP state if the corresponding
mask bit is set.
PWRHOLD
When none of the device power-on disable conditions are met, a rising edge of this signal causes an
OFF-to-ACTIVE state transition of the device and a falling edge causes a transition back to OFF state. Typically,
this signal is used to control the device in a slave configuration. It can be connected to the SYSEN output signal
from other TPS659xx devices, or the NRESPWRON signal of another TPS65910 device. This input signal is
level sensitive and no debouncing is applied.
A rising edge of PWRHOLD is highlighted though an associated interrupt.
BOOT0/BOOT1
These signals determine which processor the device is working with and hence which power-up sequence is
needed. See SWITCH-ON/-OFF SEQUENCES AND TIMING for more details. There is no debouncing on this
input signal.
NRESPWRON
This signal is used as the reset to the processor. It is held low until the ACTIVE state is reached. See POWER
CONTROL TIMING to get detailed timing.
CLK32KOUT
This signal is the output of the 32K oscillator, which can be enabled or not during the power-on sequence,
depending on the Boot mode. It can be enabled and disabled by register bit, during ACTIVE state of the device.
CLK32KOUT output can also be enabled or not during SLEEP state of the device depending on the
SLEEPMASK register programming.
PWRON
A falling edge on this signal causes after tdbPWRONF debouncing delay (defined in Figure 5 and Table 6) an
OFF-to-ACTIVE state or SLEEP-to-ACTIVE state transition of the device and makes the corresponding interrupt
(PWRON_IT) active. The PWRON input is connected to an external push-button. The built-in debouncing time
defines a minimum button press duration that is required for button press detection. Any button press duration
which is lower than this value is ignored, considered an accidental touch.
After an OFF-to-ACTIVE state transition, the PMIC maintains ACTIVE during tdOINT delay, if the button is
released. After this delay if none of the device enabling conditions is set by the processor supplied, the PMIC
automatically turns off. If the button is not released, the PMIC maintains ACTIVE up to tdPWRONLPTO, because
PWRON low is a device enabling condition. After a SLEEP-to-ACTIVE state transition, the PMIC maintains
ACTIVE as long as an interrupt is pending.
If the device is already in ACTIVE state, a PWRON low level makes the corresponding interrupt (PWRON_IT)
active.
When the PMIC is in ACTIVE mode, if the button is pressed for longer time than tdPWRONLP, the PMIC generates
the PWON_LP_IT interrupt. If the processor does not acknowledge the long press interrupt within a period of
tdPWRONLPTO – tdPWRONLP, the PMIC goes to OFF mode and shuts down the DCDCs and LDOs.
INT1
INT1 signal (default active low) warns the host processor of any event that occurred on the TPS65910 device.
The host processor can then poll the interrupt from the interrupt status register through I2C to identify the
interrupt source. A low level (default setting) indicates an active interrupt, highlighted in the INT_STS_REG
register. The polarity of INT1 can be set by programming the IT_POL control bit.
Copyright
2010–2011, Texas Instruments Incorporated
43
相关PDF资料 |
PDF描述 |
|---|---|
| TPS65921B1ZQZR | POWER SUPPLY SUPPORT CKT, PBGA120 |
| TPS65921B1ZQZ | POWER SUPPLY SUPPORT CKT, PBGA120 |
| TPS6734ID | 1.5 A SWITCHING REGULATOR, 170 kHz SWITCHING FREQ-MAX, PDSO8 |
| TPS6734IPE4 | 1.5 A SWITCHING REGULATOR, 170 kHz SWITCHING FREQ-MAX, PDIP8 |
| TPS6734IDG4 | 1.5 A SWITCHING REGULATOR, 170 kHz SWITCHING FREQ-MAX, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TPS659108A1RSL | 功能描述:PMIC 解决方案 Int Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| TPS659108A1RSLR | 功能描述:PMIC 解决方案 Int Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| TPS659108EVM-583 | 功能描述:电源管理IC开发工具 TPS659108 EVAL MOD RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| TPS659109A1RSL | 功能描述:PMIC 解决方案 Integrated Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| TPS659109A1RSLR | 功能描述:PMIC 解决方案 Integrated Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。