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参数资料
型号： TSC87C51-L16IEB
厂商： ATMEL CORP
元件分类： 微控制器/微处理器
英文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP44
封装： 1.40 MM HEIGHT, VQFP-44
文件页数： 156/176页
文件大小： 2962K
代理商： TSC87C51-L16IEB
80
2535J–AVR–08/10
ATtiny13
Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in Table 13-2 on page 80.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
13.2.3
DIDR0 – Digital Input Disable Register 0
Bits 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
Table 13-2.
ACIS1/ACIS0 Settings
ACIS1
ACIS0
Interrupt Mode
0
Comparator Interrupt on Output Toggle.
01
Reserved
1
0
Comparator Interrupt on Falling Output Edge.
1
Comparator Interrupt on Rising Output Edge.
Bit
7
65432
10
–
ADC0D
ADC2D
ADC3D
ADC1D
AIN1D
AIN0D
DIDR0
Read/Write
R
R/W
Initial Value
0
00000
00
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PDF描述
TSC87C51-20CBR 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PQCC44
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