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参数资料
| 型号： | TSPC603PMAB/C8ME |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 22/38页 |
| 文件大小： | 704K |
| 代理商： | TSPC603PMAB/C8ME |
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D Exclusive - This cache line holds valid data that is identical to the data at this address in system memory. No other cache has
this data.
D Invalid - This cache line does not hold valid data.
Cache coherency is enforced by on-chip bus snooping logic. Since the 603p’s data cache tags are single ported, a simultaneous load
or store and snoop access represent a resource contention. The snoop access is given first access to the tags. The load or store then
occurs on the clock following snoop.
Figure 16 : Data cache organization
5.4. Exception model
The following subsections describe the PowerPC exception model and the 603p implementation, respectively.
5.4.1. PowerPC exception model
The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external singles, errors, or
unusual conditions arising in the execution of instructions, and differ from the arithmetic exceptions defined by the IEEE for floating-
point operations. When exceptions occur, information about the state of the processor is saved to certain registers and the processor
begins execution at an address (exception vector) predetermined for each exception. Processing of exceptions occurs in supervisor
mode.
Although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by examin-
ing a register associated with the exception - for example, the DSISR and the FPSCR. Additionally, some exception conditions can be
explicitly enable or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order ; therefore, although a particular implementation
may recognize exception conditions out of order, they are presented strictly in order. When an instruction-caused exception is recog-
nized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute
state, are required to complete before the exception is taken. Any exceptions caused by those instructions are handled first. Likewise,
exceptions that are asynchronous and precise are recognized when they occur, but are not handled until the instruction currently in
the completion state successfully completes execution or generates an exception, and the completed store queue is emptied.
Unless a catastrophic causes a system reset or machine check exception, only one exception is handled at a time. If, for example, a
single instruction encounters multiple exception conditions, those conditions are encountered sequentially. After the exception hand-
ler handles an exception, the instruction execution continues until the next exception condition is encountered. However, in many
cases there is no attempt to re-execute the instruction. This method of recognizing and handling exception conditions sequentially
guarantees that exceptions are recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the program state from being lost due to a
system reset and machine check exception or to an instruction-caused exception in the exception handler, and before enabling exter-
nal interrupts.
The PowerPC architecture support four types of exceptions :
D Synchronous, precise - These are causes by instructions. All instruction-caused exceptions are handled precisely ; that is, the
machine state at the time the exception occurs is known and can be completely restored. This means that (excluding the trap and
system call exceptions) the address of the faulting instruction is provided to the exception handler and that neither the faulting
instruction nor subsequent instructions in the code stream will complete execution before the exception is taken. Once the excep-
tion is processed, execution resumes at the address of the faulting instruction (or at an alternate address provided by the exception
handler). When an exception is taken due to an trap or system call instruction, execution resumes at an address provided by the
handler.
D Synchronous, imprecise - The PowerPC architecture defines two imprecise floating-point exception modes, recoverable and
nonrecoverable. Even though the 603p provides a means to enable he imprecise modes, it implements these modes identically
to the precise mode (-hat is, all enabled floating-point enabled exceptions are always precise on the 603p).
相关PDF资料 |
PDF描述 |
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| TSPC603PMAB/T8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| TSPC603PVA8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| TS(X)PC603PMA6ME | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| TSPC603PVGU8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| TSPC603PVGU/T6ME | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSPC603R | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
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