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参数资料
| 型号： | TSPC603PMAB/C8ME |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 27/38页 |
| 文件大小： | 704K |
| 代理商： | TSPC603PMAB/C8ME |
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TSPC603p
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5.5. Memory management
The following subsections describe the memory management features of the PowerPC architecture, and the 603p implementation,
respectively.
5.5.1. PowerPC memory management
The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for memory accesses, and to
provide access protection on blocks and pages of memory.
There are two types of accesses generated by the 603p that require address translation - instruction accesses, and data accesses to
memory generated by load and store instructions.
The PowerPC MMU and exception model support demand-paged virtual memory. Virtual memory management permits execution of
programs larger than the size of physical memory ; demand-paged implies that individual pages are loaded into physical memory
from system memory only when they are first accessed by an executing program.
The hashed page table is a variable-sized data structure that defines the mapping between virtual page numbers and physical page
numbers. The page table size is a power of 2, and its starting address is a multiple of its size.
The page table contains a number of page table entry groups (PTEGs). A PTEG contains eight page table entries (PTEs) of eight
bytes each ; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table search operations.
Address translations are enabled by setting bits in the MSR-MSR[IR] enables instruction address translations and MSR[DR] enables
data address translations.
5.5.2. PowerPC 603p microprocessor memory management
The instruction and data memory management units in the 603p provide 4 Gbyte of logical address space accessible to supervisor
and user programs with a 4-Kbyte page size and 256-Mbyte segment size. Block sizes range from 128 Kbyte to 256Mbyte and are
software selectable. In addition, the 603p uses an interim 52-bit virtual address and hashed page tables for generating 32-bit physical
addresses. The MMUs in the 603p rely on the exception processing mechanism for the implementation of the paged virtual memory
environment and for enforcing protection of designated memory areas.
Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring no additional time penalty in
the event of a TLB hit. A TLB is a cache of the most recently used page table entries. Software is responsible for maintaining the
consistency of the TLB with memory. The 603p’s TLBs are 64-entry, two-way set-associative caches that contain instruction and data
address translations. The 603p provides hardware assist for software table search operations through the ashed page table on TLB
misses. Supervisor software can invalidate TLB entries selectively.
The 603p also provides independent four-entry BAT arrays for instructions and data that maintain address translations for blocks of
memory. These entries define blocks that can vary from 128 Kbyte to 256 Mbyte. The BAT arrays are maintained by system software.
As specified by the PowerPC architecture, the hashed page table is a variable-sized data structure that defines the mapping between
virtual page numbers and physical page numbers. The page table size is a power of 2, and its starting address is a multiple of its size.
Also as specified by the PowerPC architecture, the page table contains a number of page table entry groups (PTEGs). A PTEG con-
tains eight page table entries (PTEs) of eight bytes each ; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for
table search operations.
5.6. Instruction timing
The 603p is a pipelined superscalar processor. A pipelined processor is one in which the processing of an instruction is reduced into
discrete stages. Because the processing of an instruction is broken into a series of stages, an instruction does not require the entire
resources of an execution unit. For example, after an instruction completes the decode stage, it can pass on to the next stage, while
the subsequent instruction can advance into the decode stage. This improves the throughput of the instruction flow. For example, it
may take three cycles for a floating-point instruction to complete, but if there are no stalls in the floating-point pipeline, a series of
floating-point instructions can have a throughput of one instruction per cycle.
相关PDF资料 |
PDF描述 |
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| TSPC603PMAB/T8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| TSPC603PVA8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| TS(X)PC603PMA6ME | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| TSPC603PVGU8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSPC603R | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
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