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参数资料
| 型号： | TSPC603PMAB/C8ME |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 38/38页 |
| 文件大小： | 704K |
| 代理商： | TSPC603PMAB/C8ME |
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TSPC603p
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Table 3 : Address and data bus signal index
Signal name
Mnemonic
Signal function
Signal
type
Address bus
A[0-31]
if output, physical address of data to be transferred.
if input, represents the physical address of a snoop operation.
I/O
Data bus
DH[0-31]
Represents the state of data, during a data write operation if output, or
during a data read operation if input.
I/O
Data bus
DL[0-31]
Represents the state of data, during a data write operation if output, or
during a data read operation if input.
I/O
Table 4 : Signal index
Signal name
Mnemonic
Signal function
Signal
type
Address Acknowledge
AACK
The address phase of a transaction is complete
Input
Address Bus Busy
ABB
If output, the 603p is the address bus master
If input, the address bus is in use
I/O
Address Bus Parity
AP[0-3]
If output, represents odd parity for each of 4 bytes of the physical
address for a transaction
If input, represents odd parity for each of 4 bytes of the physical address
for snooping operations
I/O
Address Parity Error
APE
Incorrect address bus parity detected on a snoop
Output
Address retry
ARTRY
If output, detects a condition in which a snooped address tenure must be
retried
If input, must retry the preceding address tenure
I/O
Bus grant
BG
May, with the proper qualification, assume mastership of the address
bus
Input
Bus request
BR
Request mastership of the address bus
Output
Cache Inhibit
Cl
A single-beat transfer will not be cached
Output
Test Clock
CLK_OUT
Provides PLL clock output for PLL testing and monitoring
Output
Checkstop Input
CKSTP_IN
Must terminate operation by internally gating off all clocks, and release
all outputs
Input
Checkstop Output
CKSTP_OUT
Has detected a checkstop condition and has ceased operation
Output
Cache Set Entry
CSE[0-1]
Cache replacement set element for the current transaction reloading into
or writing out of the cache
Output
Data Bus Busy
DBB
If output, the 603p is the data bus master
If input, another device is bus master
I/O
Data Bus Disable
DBDIS
(For a write transaction) must release data bus and the data bus parity
to high impedance during the following cycle
Input
Data Bus Grant
DBG
May, with the proper qualification, assume mastership of the data bus
Input
Data Bus Write Only
DBW0
May run the data bus tenure
Input
Data Bus Parity
DP[0-7]
If output, odd parity for each of 8 bytes of data write transactions
If input, odd parity for each byte of read data
I/O
Data Parity Error
DPE
Incorrect data bus parity
Output
Data Retry
DRTRY
Must invalidate the data from the previous read operation
Input
Global
GBL
If output, a transaction is global
If input, a transaction must be snooped by the 603p
I/O
Hard Reset
HRESET
Initiates a complete hard reset operation
Input
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSPC603R | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
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