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参数资料
| 型号： | TVP5150AEVM |
| 厂商： | Texas Instruments |
| 文件页数： | 14/74页 |
| 文件大小： | 0K |
| 描述： | TVP5150AEVM |
| 标准包装： | 1 |
| 主要目的： | 视频，视频解码器 |
| 已用 IC / 零件： | TVP5150A |
| 主要属性： | NTSC/PAL 数字视频解码器 |
| 次要属性： | 图形用户接口，I²C 接口 |
| 已供物品： | 2 个板，线缆，CD，电源 |
| 配用： | 296-23058-ND - EVAL MODULE FOR DM642 |
| 相关产品： | TVP5150PBSR-ND - IC NTSC/PAL/SECAM DECODER 32TQFP TVP5150APBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP TVP5150AM1ZQCR-ND - IC VIDEO DECODER 8BIT 48BGA TVP5150AM1PBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP TVP5150AM1PBSG4-ND - IC VIDEO DECODER 8BIT 32TQFP 296-32781-ND - IC VIDEO DECODER 8BIT 32TQFP 296-32780-ND - IC VIDEO DECODER 8BIT 48BGA 296-27133-ND - IC VIDEO DECODER 8BIT 32TQFP 296-23026-6-ND - IC VIDEO DECODER 48-BGA 296-23025-6-ND - IC VIDEO DECODER 32-TQFP 更多... |
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2.15.2.2 Read Phase 2
Step 7
0
I2C Start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
0
X
1
Step 9
9
I2C Acknowledge (slave)
A
Step 10
7
6
5
4
3
2
1
0
I2C Read data (slave)
Data
Step 11
9
I2C Not acknowledge (master)
A
Step 12
0
I2C Stop (master)
P
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
2.15.2.3 I2C Timing Requirements
The TVP5150A decoder requires delays in the I2C accesses to accommodate its internal processor’s timing. In
accordance with I2C specifications, the TVP5150A decoder holds the I2C clock line (SCL) low to indicate the wait
period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the
maximum delays must always be inserted where required. These delays are of variable length; maximum delays are
indicated in the following diagram:
Normal register writing address 00h8Fh (addresses 90hFFh do not require delays)
Start
Slave address
(B8h)
Ack
Subaddress
Ack
Data
(XXh)
Ack
Wait 64
s
Stop
2.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL.
This may be input to the TVP5150A decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental
resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 25 shows the reference clock
configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental
frequency), the external capacitors must have the following relationship:
CL1 = CL2 = 2CL CSTRAY,
where CSTRAY is the terminal capacitance with respect to ground. Figure 25 shows the reference clock
configurations.
TVP5150A
5
XTAL1
14.31818-MHz
Crystal
6
XTAL2
TVP5150A
5
XTAL1
6
XTAL2
CL1
CL2
14.31818-MHz
TTL Clock
Figure 25. Reference Clock Configurations
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TVP5150AM1 | 制造商:Texas Instruments 功能描述:Ultra-low Power Video Decoder TVP5150AM1 |
| TVP5150AM1-EP | 制造商:TI 制造商全称:Texas Instruments 功能描述:Ultralow-Power NTSC/PAL/SECAM Video Decoder |
| TVP5150AM1IPBS | 功能描述:视频 IC Ultralow Pwr NTSC PAL/SECAM Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| TVP5150AM1IPBS | 制造商:Texas Instruments 功能描述:IC VIDEO DECODER 9BIT 30MSPS TQFP-32 制造商:Texas Instruments 功能描述:IC, VIDEO DECODER, 9BIT, 30MSPS, TQFP-32 |
| TVP5150AM1IPBSQ1 | 功能描述:视频 IC UltraLo Pwr NTSC/ PAL/SECAM Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
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