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参数资料
| 型号： | TVP5150AEVM |
| 厂商： | Texas Instruments |
| 文件页数： | 21/74页 |
| 文件大小： | 0K |
| 描述： | TVP5150AEVM |
| 标准包装： | 1 |
| 主要目的： | 视频，视频解码器 |
| 已用 IC / 零件： | TVP5150A |
| 主要属性： | NTSC/PAL 数字视频解码器 |
| 次要属性： | 图形用户接口，I²C 接口 |
| 已供物品： | 2 个板，线缆，CD，电源 |
| 配用： | 296-23058-ND - EVAL MODULE FOR DM642 |
| 相关产品： | TVP5150PBSR-ND - IC NTSC/PAL/SECAM DECODER 32TQFP TVP5150APBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP TVP5150AM1ZQCR-ND - IC VIDEO DECODER 8BIT 48BGA TVP5150AM1PBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP TVP5150AM1PBSG4-ND - IC VIDEO DECODER 8BIT 32TQFP 296-32781-ND - IC VIDEO DECODER 8BIT 32TQFP 296-32780-ND - IC VIDEO DECODER 8BIT 48BGA 296-27133-ND - IC VIDEO DECODER 8BIT 32TQFP 296-23026-6-ND - IC VIDEO DECODER 48-BGA 296-23025-6-ND - IC VIDEO DECODER 32-TQFP 更多... |
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218
2.20.4 Miscellaneous Control Register
Address
03h
Default
01h
7
6
5
4
3
2
1
0
VBKO
GPCL pin
GPCL I/O mode
select
Lock status
(HVLK)
YCbCr output
enable (TVPOE)
HSYNC, VSYNC/PALI,
AVID, FID/GLCO
output enable
Vertical blanking
on/off
Clock output
enable
VBKO (pin 27) function select:
0 = GPCL (default)
1 = VBLK
GPCL (data is output based on state of bit 5):
0 = GPCL outputs 0 (default)
1 = GPCL outputs 1
GPCL I/O mode select:
0 = GPCL is input (default)
1 = GPCL is output
Lock status (HVLK) (configured along with register 0Fh, please see Figure 28 for the relationship between the
configuration shared pins):
0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the field
ID (FID) signal (default) (if terminals are configured to output PALI and FID in register 0Fh)
1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the vertical
lock indicator (VLK) (if terminals are configured to output PALI and FID in register 0Fh)
These are additional functionalities that are provided for ease of use.
YCbCr output enable:
0 = Y(OUT7:0) high impedance (default)
1 = Y(OUT7:0) active
HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables:
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high-impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
Vertical blanking on/off:
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
Clock output enable:
0 = SCLK output is high impedance.
1 = SCLK output is enabled (default).
NOTE: When enabling the outputs, ensure the clock output is not accidently disabled.
Table 211. Digital Output Control
Register 03h, Bit 3
(TVPOE)
Register C2h, Bit 2
(VDPOE)
YCbCr Output
Notes
0
X
High impedance
After both YCbCr output enable bits are programmed.
X
0
High impedance
After both YCbCr output enable bits are programmed.
1
Active
After both YCbCr output enable bits are programmed.
NOTE: VDPOE default is 1 and TVPOE default is 0.
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